Fix initialization of "irq" in verilog testbench

Signed-off-by: Clifford Wolf <clifford@clifford.at>

testbench.v

@@ -75,7 +75,7 @@ module picorv32_wrapper #(
 	output [35:0] trace_data
 );
 	wire tests_passed;
-	reg [31:0] irq;
+	reg [31:0] irq = 0;
 
 	reg [15:0] count_cycle = 0;
 	always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;

testbench_wb.v

@@ -65,7 +65,7 @@ module picorv32_wrapper #(
 	output [35:0] trace_data
 );
 	wire tests_passed;
-	reg [31:0] irq;
+	reg [31:0] irq = 0;
 	wire mem_instr;
 
 	reg [15:0] count_cycle = 0;