From 42e498aa28507590e1d035ab1336360b5ecc358f Mon Sep 17 00:00:00 2001 From: "colin.liang" Date: Tue, 10 Jan 2023 15:43:08 +0800 Subject: [PATCH] mv from picorv to testbench --- picorv32.v | 173 ------------------------------------------------- testbench_wb.v | 160 +++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 148 insertions(+), 185 deletions(-) diff --git a/picorv32.v b/picorv32.v index 42c6094..3f3d0bc 100644 --- a/picorv32.v +++ b/picorv32.v @@ -2218,176 +2218,3 @@ module picorv32_pcpi_div ( end end endmodule - - -/*************************************************************** - * picorv32_wb - ***************************************************************/ - -module picorv32_wb #( - parameter [ 0:0] ENABLE_COUNTERS = 1, - parameter [ 0:0] ENABLE_COUNTERS64 = 1, - parameter [ 0:0] ENABLE_REGS_16_31 = 1, - parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, - parameter [ 0:0] TWO_STAGE_SHIFT = 1, - parameter [ 0:0] BARREL_SHIFTER = 0, - parameter [ 0:0] TWO_CYCLE_COMPARE = 0, - parameter [ 0:0] TWO_CYCLE_ALU = 0, - parameter [ 0:0] COMPRESSED_ISA = 0, - parameter [ 0:0] CATCH_MISALIGN = 1, - parameter [ 0:0] CATCH_ILLINSN = 1, - parameter [ 0:0] ENABLE_PCPI = 0, - parameter [ 0:0] ENABLE_MUL = 0, - parameter [ 0:0] ENABLE_FAST_MUL = 0, - parameter [ 0:0] ENABLE_DIV = 0, - parameter [ 0:0] ENABLE_IRQ = 0, - parameter [ 0:0] ENABLE_IRQ_QREGS = 1, - parameter [ 0:0] ENABLE_IRQ_TIMER = 1, - parameter [ 0:0] ENABLE_TRACE = 0, - parameter [ 0:0] REGS_INIT_ZERO = 0, - parameter [31:0] MASKED_IRQ = 32'h 0000_0000, - parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, - parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, - parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, - parameter [31:0] STACKADDR = 32'h ffff_ffff -) ( - output trap, - output reg exit, - - // Wishbone interfaces - input wb_rst_i, - input wb_clk_i, - - output reg [31:0] wbm_adr_o, - output reg [31:0] wbm_dat_o, - input [31:0] wbm_dat_i, - output reg wbm_we_o, - output reg [3:0] wbm_sel_o, - output reg wbm_stb_o, - input wbm_ack_i, - output reg wbm_cyc_o, - - // Pico Co-Processor Interface (PCPI) - output pcpi_valid, - output [31:0] pcpi_insn, - output [31:0] pcpi_rs1, - output [31:0] pcpi_rs2, - input pcpi_wr, - input [31:0] pcpi_rd, - input pcpi_wait, - input pcpi_ready, - - // IRQ interface - input [31:0] irq, - output [31:0] eoi, - - // Trace Interface - output trace_valid, - output [35:0] trace_data, - - output mem_instr -); - wire mem_valid; - wire [31:0] mem_addr; - wire [31:0] mem_wdata; - wire [ 3:0] mem_wstrb; - reg mem_ready; - reg [31:0] mem_rdata; - - wire mem_la_read; - wire mem_la_write; - wire [31:0] mem_la_addr; - wire [31:0] mem_la_wdata; - wire [3:0] mem_la_wstrb; - - - wire clk; - wire resetn; - initial exit = 0; - - assign clk = wb_clk_i; - assign resetn = ~wb_rst_i; - - picorv32 #( - .ENABLE_COUNTERS (ENABLE_COUNTERS ), - .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), - .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), - .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), - .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), - .BARREL_SHIFTER (BARREL_SHIFTER ), - .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), - .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), - .COMPRESSED_ISA (COMPRESSED_ISA ), - .CATCH_MISALIGN (CATCH_MISALIGN ), - .CATCH_ILLINSN (CATCH_ILLINSN ), - .ENABLE_PCPI (ENABLE_PCPI ), - .ENABLE_MUL (ENABLE_MUL ), - .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), - .ENABLE_DIV (ENABLE_DIV ), - .ENABLE_IRQ (ENABLE_IRQ ), - .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), - .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), - .ENABLE_TRACE (ENABLE_TRACE ), - .REGS_INIT_ZERO (REGS_INIT_ZERO ), - .MASKED_IRQ (MASKED_IRQ ), - .LATCHED_IRQ (LATCHED_IRQ ), - .PROGADDR_RESET (PROGADDR_RESET ), - .PROGADDR_IRQ (PROGADDR_IRQ ), - .STACKADDR (STACKADDR ) - ) picorv32_core ( - .clk (clk ), - .resetn (resetn), - .trap (trap ), - - - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ), - .mem_la_read (mem_la_read ), - .mem_la_write(mem_la_write), - .mem_la_addr (mem_la_addr ), - .mem_la_wdata(mem_la_wdata), - .mem_la_wstrb(mem_la_wstrb), - .irq(irq), - .eoi(eoi), - - .trace_valid(trace_valid), - .trace_data (trace_data) - ); - - - reg [7:0] memory [0:256*1024-1]; - - assign mem_ready = 1; - - always @(posedge clk) begin - mem_rdata[ 7: 0] <= mem_la_read ? memory[mem_la_addr + 0] : 'bx; - mem_rdata[15: 8] <= mem_la_read ? memory[mem_la_addr + 1] : 'bx; - mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr + 2] : 'bx; - mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr + 3] : 'bx; - if (mem_la_write) begin - case (mem_la_addr) - 32'h1000_0000: begin -`ifndef TIMING - $write("%c", mem_la_wdata); - $fflush(); -`endif - end - 32'h2000_0000: begin - if (mem_la_wdata[31:0] == 123456789) - exit = 1; - end - default: begin - if (mem_la_wstrb[0]) memory[mem_la_addr + 0] <= mem_la_wdata[ 7: 0]; - if (mem_la_wstrb[1]) memory[mem_la_addr + 1] <= mem_la_wdata[15: 8]; - if (mem_la_wstrb[2]) memory[mem_la_addr + 2] <= mem_la_wdata[23:16]; - if (mem_la_wstrb[3]) memory[mem_la_addr + 3] <= mem_la_wdata[31:24]; - end - endcase - end - end -endmodule diff --git a/testbench_wb.v b/testbench_wb.v index 80dce12..6cfcdaf 100644 --- a/testbench_wb.v +++ b/testbench_wb.v @@ -87,18 +87,6 @@ module picorv32_wrapper #( wire wb_s2m_ack; picorv32_wb #( -`ifndef SYNTH_TEST -`ifdef SP_TEST - .ENABLE_REGS_DUALPORT(0), -`endif -`ifdef COMPRESSED_ISA - .COMPRESSED_ISA(1), -`endif - .ENABLE_MUL(1), - .ENABLE_DIV(1), - .ENABLE_IRQ(1), - .ENABLE_TRACE(1) -`endif ) uut ( .trap (trap), .exit(exit), @@ -138,3 +126,151 @@ module picorv32_wrapper #( end end endmodule + + + +/*************************************************************** + * picorv32_wb + ***************************************************************/ + + module picorv32_wb #() ( + output trap, + output reg exit, + + // Wishbone interfaces + input wb_rst_i, + input wb_clk_i, + + output reg [31:0] wbm_adr_o, + output reg [31:0] wbm_dat_o, + input [31:0] wbm_dat_i, + output reg wbm_we_o, + output reg [3:0] wbm_sel_o, + output reg wbm_stb_o, + input wbm_ack_i, + output reg wbm_cyc_o, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + + // Trace Interface + output trace_valid, + output [35:0] trace_data, + + output mem_instr +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + reg mem_ready; + reg [31:0] mem_rdata; + + wire mem_la_read; + wire mem_la_write; + wire [31:0] mem_la_addr; + wire [31:0] mem_la_wdata; + wire [3:0] mem_la_wstrb; + + + wire clk; + wire resetn; + initial exit = 0; + + assign clk = wb_clk_i; + assign resetn = ~wb_rst_i; + + picorv32 #( + .ENABLE_COUNTERS(1), + .ENABLE_COUNTERS64(1), + .ENABLE_REGS_16_31(1), + .ENABLE_REGS_DUALPORT(1), + .TWO_STAGE_SHIFT(1), + .BARREL_SHIFTER(0), + .TWO_CYCLE_COMPARE(0), + .TWO_CYCLE_ALU(0), + .COMPRESSED_ISA(1), + .CATCH_MISALIGN(0), + .CATCH_ILLINSN(1), + .ENABLE_PCPI(0), + .ENABLE_MUL(1), + .ENABLE_FAST_MUL(0), + .ENABLE_DIV(1), + .ENABLE_IRQ(1), + .ENABLE_IRQ_QREGS(1), + .ENABLE_IRQ_TIMER(1), + .ENABLE_TRACE(1), + .REGS_INIT_ZERO(0), + .MASKED_IRQ(32'h 0000_0000), + .LATCHED_IRQ(32'h ffff_ffff), + .PROGADDR_RESET(32'h 0000_0000), + .PROGADDR_IRQ(32'h 0000_0010), + .STACKADDR(32'h ffff_ffff) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ), + .mem_la_read (mem_la_read ), + .mem_la_write(mem_la_write), + .mem_la_addr (mem_la_addr ), + .mem_la_wdata(mem_la_wdata), + .mem_la_wstrb(mem_la_wstrb), + .irq(irq), + .eoi(eoi), + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); + + + reg [7:0] memory [0:256*1024-1]; + + assign mem_ready = 1; + + always @(posedge clk) begin + mem_rdata[ 7: 0] <= mem_la_read ? memory[mem_la_addr + 0] : 'bx; + mem_rdata[15: 8] <= mem_la_read ? memory[mem_la_addr + 1] : 'bx; + mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr + 2] : 'bx; + mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr + 3] : 'bx; + if (mem_la_write) begin + case (mem_la_addr) + 32'h1000_0000: begin +`ifndef TIMING + $write("%c", mem_la_wdata); + $fflush(); +`endif + end + 32'h2000_0000: begin + if (mem_la_wdata[31:0] == 123456789) + exit = 1; + end + default: begin + if (mem_la_wstrb[0]) memory[mem_la_addr + 0] <= mem_la_wdata[ 7: 0]; + if (mem_la_wstrb[1]) memory[mem_la_addr + 1] <= mem_la_wdata[15: 8]; + if (mem_la_wstrb[2]) memory[mem_la_addr + 2] <= mem_la_wdata[23:16]; + if (mem_la_wstrb[3]) memory[mem_la_addr + 3] <= mem_la_wdata[31:24]; + end + endcase + end + end +endmodule