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Fix decoding of C.ADDI instruction 

See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts
for discussion. There was a bug in the ISA manual.
This commit is contained in:
Clifford Wolf 2017-05-13 12:28:54 +02:00
parent cd30db3425
commit 436544ccab
1 changed files with 3 additions and 5 deletions
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2
picorv32.v
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@ -890,12 +890,10 @@ module picorv32 #(
2'b01: begin // Quadrant 1 2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13]) case (mem_rdata_latched[15:13])
3'b000: begin // C.NOP / C.ADDI 3'b000: begin // C.NOP / C.ADDI
if (!mem_rdata_latched[12:2] || mem_rdata_latched[11:7]) begin
is_alu_reg_imm <= 1; is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7]; decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7]; decoded_rs1 <= mem_rdata_latched[11:7];
end end
end
3'b001: begin // C.JAL 3'b001: begin // C.JAL
instr_jal <= 1; instr_jal <= 1;
decoded_rd <= 1; decoded_rd <= 1;