Updates dhrystone results

README.md

@@ -289,9 +289,12 @@ a core built without ENABLE_REGS_DUALPORT.
 When `ENABLE_MUL` is activated, then a `MUL` instruction will execute
 in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles.
 
-Dhrystone benchmark results: 0.327 DMIPS/MHz (575 Dhrystones/Second/MHz)
+When `ENABLE_DIV` is activated, then a `DIV[U]/REM[U]` instruction will
+execute in 40 cycles.
 
-For the Dhrystone benchmark the average CPI is 3.945.
+Dhrystone benchmark results: 0.391 DMIPS/MHz (688 Dhrystones/Second/MHz)
+
+For the Dhrystone benchmark the average CPI is 4.110.
 
 
 PicoRV32 Native Memory Interface

dhrystone/Makefile

@@ -1,6 +1,6 @@
 
 OBJS = start.o dhry_1.o dhry_2.o stdlib.o
-CFLAGS = -MD -O3 -m32 -march=RV32I -ffreestanding -nostdlib -DTIME -DRISCV
+CFLAGS = -MD -O3 -m32 -march=RV32IM -ffreestanding -nostdlib -DTIME -DRISCV
 TOOLCHAIN_PREFIX = riscv32-unknown-elf-
 
 test: testbench.exe dhry.hex
@@ -8,7 +8,7 @@ test: testbench.exe dhry.hex
 
 timing: timing.exe dhry.hex
 	vvp -N timing.exe > timing.txt
-	sed 's,.*## ,,' timing.txt | gawk 'x != "" {print x,$$2-y;} {x=$$1;y=$$2;}' | sort | uniq -c | sort -k3 -n
+	grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | sort -k3 -n
 
 testbench.exe: testbench.v ../picorv32.v
 	iverilog -o testbench.exe testbench.v ../picorv32.v

dhrystone/testbench.v

@@ -26,7 +26,10 @@ module testbench;
 	wire [31:0] mem_la_wdata;
 	wire [3:0] mem_la_wstrb;
 
-	picorv32 uut (
+	picorv32 #(
+		.ENABLE_MUL(1),
+		.ENABLE_DIV(1)
+	) uut (
 		.clk         (clk        ),
 		.resetn      (resetn     ),
 		.trap        (trap       ),
@@ -88,7 +91,7 @@ module testbench;
 		$finish;
 	end
 	always @(uut.count_instr[0]) begin
-		$display("## %-s %d", uut.instruction, uut.count_cycle);
+		$display("## %-s %d", uut.ascii_instr ? uut.ascii_instr : "x", uut.count_cycle);
 	end
 `endif
 endmodule