colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update picosoc memory map

This commit is contained in:
Clifford Wolf 2017-09-15 14:47:50 +02:00
parent a412d3ea69
commit 48b13daef2
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
picosoc/README.md
View File

@ -38,6 +38,9 @@ and upload them to a connected iCE40-HX8K Breakout Board.
| 0x02000008 .. 0x0200000B | UART Send/Recv Data Register | | 0x02000008 .. 0x0200000B | UART Send/Recv Data Register |
| 0x03000000 .. 0xFFFFFFFF | Memory mapped user peripherals | | 0x03000000 .. 0xFFFFFFFF | Memory mapped user peripherals |
The addresses in the internal SRAM region beyond the end of the physical
SRAM map to the corresponding addresses in serial flash.
Reading from the UART Send/Recv Data Register will return the last received Reading from the UART Send/Recv Data Register will return the last received
byte, or -1 (all 32 bits set) when the receive buffer is empty. byte, or -1 (all 32 bits set) when the receive buffer is empty.

8
picosoc/picosoc.v
View File

@ -51,7 +51,7 @@ module picosoc (
); );
parameter integer MEM_WORDS = 256; parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0110_0000; // 1 MB into flash parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
wire mem_valid; wire mem_valid;
wire mem_instr; wire mem_instr;
@ -87,7 +87,7 @@ module picosoc (
assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata : assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do : spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h xxxx_xxxx; simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
picorv32 #( picorv32 #(
.STACKADDR(STACKADDR), .STACKADDR(STACKADDR),
@ -107,7 +107,7 @@ module picosoc (
spimemio spimemio ( spimemio spimemio (
.clk (clk), .clk (clk),
.resetn (resetn), .resetn (resetn),
.valid (mem_valid && mem_addr[31:24] == 8'h 01), .valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
.ready (spimem_ready), .ready (spimem_ready),
.addr (mem_addr[23:0]), .addr (mem_addr[23:0]),
.rdata (spimem_rdata), .rdata (spimem_rdata),
@ -157,7 +157,7 @@ module picosoc (
always @(posedge clk) begin always @(posedge clk) begin
ram_ready <= 0; ram_ready <= 0;
if (mem_valid && !mem_ready && mem_addr[31:24] == 8'h 00) begin if (mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) begin
ram_ready <= 1; ram_ready <= 1;
ram_rdata <= memory[mem_addr >> 2]; ram_rdata <= memory[mem_addr >> 2];
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];