Added (set-info ..) generation to smtio.py
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@ -62,7 +62,7 @@ def timestamp():
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return "+ %6d [%3d:%02d:%02d] " % (secs, secs // (60*60), (secs // 60) % 60, secs % 60)
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print("Solver: %s" % solver)
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smt.write("(set-logic QF_AUFBV)")
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smt.setup("QF_AUFBV", "PicoRV32 \"async.py\" BMC script, powered by Yosys")
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regs_a = list()
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regs_b = list()
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@ -135,9 +135,7 @@ for step in range(steps):
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else:
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assert False
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smt.write("(check-sat)")
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if smt.read() == "sat":
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if smt.check_sat() == "sat":
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print("%s Creating model.." % timestamp())
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@ -149,8 +147,6 @@ for step in range(steps):
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make_cpu_regs(0)
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make_cpu_regs(step)
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smt.write("(check-sat)")
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def print_status(mod, step):
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resetn = smt.get_net_bool("main_" + mod, "resetn", "%s%d" % (mod, step))
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memvld = smt.get_net_bool("main_" + mod, "mem_valid", "%s%d" % (mod, step))
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@ -176,7 +172,7 @@ for step in range(steps):
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rb = smt.bv2hex(smt.get("b%d_r%d" % (step, i)))
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print("%3s[%d]: A=%s B=%s%s" % ("x%d" % i, step, ra, rb, " !" if ra != rb else ""))
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assert smt.read() == "sat"
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assert smt.check_sat() == "sat"
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if initzero:
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for rn, rs in regs_a:
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@ -188,8 +184,7 @@ for step in range(steps):
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smt.write("(assert (not (|main_a_n %s| a0)))" % rn)
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else:
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smt.write("(assert (= (|main_a_n %s| a0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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if smt.read() != "sat":
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if smt.check_sat() != "sat":
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force_to_zero = False
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smt.write("(pop 1)")
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if force_to_zero:
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@ -197,8 +192,7 @@ for step in range(steps):
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smt.write("(assert (not (|main_a_n %s| a0)))" % rn)
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else:
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smt.write("(assert (= (|main_a_n %s| a0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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assert smt.read() == "sat"
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assert smt.check_sat() == "sat"
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for rn, rs in regs_b:
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force_to_zero = True
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if smt.get_net_bin("main_b", rn, "b0").count("1") != 0:
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@ -208,8 +202,7 @@ for step in range(steps):
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smt.write("(assert (not (|main_b_n %s| b0)))" % rn)
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else:
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smt.write("(assert (= (|main_b_n %s| b0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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if smt.read() != "sat":
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if smt.check_sat() != "sat":
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force_to_zero = False
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smt.write("(pop 1)")
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if force_to_zero:
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@ -217,8 +210,7 @@ for step in range(steps):
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smt.write("(assert (not (|main_b_n %s| b0)))" % rn)
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else:
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smt.write("(assert (= (|main_b_n %s| b0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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assert smt.read() == "sat"
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assert smt.check_sat() == "sat"
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print()
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print_cpu_regs(0)
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@ -21,6 +21,13 @@ class smtio:
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self.debug_file = debug_file
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self.p = subprocess.Popen(popen_vargs, stdin=subprocess.PIPE, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
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def setup(self, logic="ALL", info=None):
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self.write("(set-logic %s)" % logic)
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if info is not None:
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self.write("(set-info :source |%s|)" % info)
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self.write("(set-info :smt-lib-version 2.5)")
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self.write("(set-info :category \"industrial\")")
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def write(self, stmt):
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stmt = stmt.strip()
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if self.debug_print:
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@ -55,6 +62,21 @@ class smtio:
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return stmt
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def check_sat(self):
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if self.debug_print:
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print("> (check-sat)")
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if self.debug_file:
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print("; running check-sat..", file=self.debug_file)
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self.debug_file.flush()
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self.p.stdin.write(bytes("(check-sat)\n", "ascii"))
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self.p.stdin.flush()
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result = self.read()
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if self.debug_file:
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print("(set-info :status %s)" % result, file=self.debug_file)
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print("(check-sat)", file=self.debug_file)
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self.debug_file.flush()
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return result
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def parse(self, stmt):
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def worker(stmt):
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if stmt[0] == '(':
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@ -58,7 +58,7 @@ def timestamp():
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return "+ %6d [%3d:%02d:%02d] " % (secs, secs // (60*60), (secs // 60) % 60, secs % 60)
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print("Solver: %s" % solver)
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smt.write("(set-logic QF_AUFBV)")
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smt.setup("QF_AUFBV", "PicoRV32 \"sync.py\" BMC script, powered by Yosys")
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regs_a = list()
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regs_b = list()
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@ -108,9 +108,8 @@ for step in range(steps):
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smt.write(("(assert (or (distinct (|main_a_m cpu.cpuregs| a%d) (|main_b_m cpu.cpuregs| b%d)) " +
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"(distinct (|main_a_m memory| a%d) (|main_b_m memory| b%d))" +
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"(distinct (|main_a_n trap| a%d) (|main_b_n trap| b%d))))") % (step, step, step, step, step, step))
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smt.write("(check-sat)")
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if smt.read() == "sat":
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if smt.check_sat() == "sat":
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print("%s Creating model.." % timestamp())
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@ -122,8 +121,7 @@ for step in range(steps):
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make_cpu_regs(0)
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make_cpu_regs(step)
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smt.write("(check-sat)")
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assert smt.read() == "sat"
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assert smt.sheck_sat() == "sat"
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def print_status(mod, step):
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resetn = smt.get_net_bool("main_" + mod, "resetn", "%s%d" % (mod, step))
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