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Format code.

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colin.liang 2023-01-12 17:22:59 +08:00
parent 665f26dc63
commit 4beed17d0a
1 changed files with 1376 additions and 1397 deletions
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picorv32.v
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@ -30,9 +30,9 @@
// `define DEBUG // `define DEBUG
`ifdef DEBUG `ifdef DEBUG
`define debug(debug_command) debug_command `define debug(debug_command) debug_command
`else `else
`define debug(debug_command) `define debug(debug_command)
`endif `endif
`define assert(assert_expr) empty_statement `define assert(assert_expr) empty_statement
@ -43,18 +43,19 @@
***************************************************************/ ***************************************************************/
module picorv32 #( module picorv32 #(
parameter [ 0:0] TWO_STAGE_SHIFT = 1, parameter [0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0, parameter [0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0, parameter [0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0, parameter [0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] ENABLE_TRACE = 0, parameter [0:0] ENABLE_TRACE = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] MASKED_IRQ = 32'h0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] LATCHED_IRQ = 32'hffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, parameter [31:0] PROGADDR_RESET = 32'h0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, parameter [31:0] PROGADDR_IRQ = 32'h0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff parameter [31:0] STACKADDR = 32'hffff_ffff
) ( ) (
input clk, resetn, input clk,
resetn,
output reg trap, output reg trap,
output reg mem_valid, output reg mem_valid,
@ -98,9 +99,9 @@ module picorv32 #(
localparam integer irqregs_offset = 32; localparam integer irqregs_offset = 32;
localparam integer regfile_size = 32 + 4; localparam integer regfile_size = 32 + 4;
localparam integer regindex_bits = 5 + 1; localparam integer regindex_bits = 5 + 1;
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; localparam [35:0] TRACE_BRANCH = {4'b0001, 32'b0};
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0}; localparam [35:0] TRACE_ADDR = {4'b0010, 32'b0};
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0}; localparam [35:0] TRACE_IRQ = {4'b1000, 32'b0};
reg [63:0] count_cycle, count_instr; reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out; reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
@ -115,7 +116,7 @@ module picorv32 #(
wire dbg_mem_ready = mem_ready; wire dbg_mem_ready = mem_ready;
wire [31:0] dbg_mem_addr = mem_addr; wire [31:0] dbg_mem_addr = mem_addr;
wire [31:0] dbg_mem_wdata = mem_wdata; wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb; wire [3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata; wire [31:0] dbg_mem_rdata = mem_rdata;
assign pcpi_rs1 = reg_op1; assign pcpi_rs1 = reg_op1;
@ -132,7 +133,8 @@ module picorv32 #(
task empty_statement; task empty_statement;
// This task is used by the `assert directive in non-formal mode to // This task is used by the `assert directive in non-formal mode to
// avoid empty statement (which are unsupported by plain Verilog syntax). // avoid empty statement (which are unsupported by plain Verilog syntax).
begin end begin
end
endtask endtask
// Internal PCPI Cores // Internal PCPI Cores
@ -154,29 +156,29 @@ module picorv32 #(
picorv32_pcpi_mul pcpi_mul ( picorv32_pcpi_mul pcpi_mul (
.clk (clk ), .clk (clk),
.resetn (resetn ), .resetn (resetn),
.pcpi_valid(pcpi_valid ), .pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ), .pcpi_insn (pcpi_insn),
.pcpi_rs1 (pcpi_rs1 ), .pcpi_rs1 (pcpi_rs1),
.pcpi_rs2 (pcpi_rs2 ), .pcpi_rs2 (pcpi_rs2),
.pcpi_wr (pcpi_mul_wr ), .pcpi_wr (pcpi_mul_wr),
.pcpi_rd (pcpi_mul_rd ), .pcpi_rd (pcpi_mul_rd),
.pcpi_wait (pcpi_mul_wait ), .pcpi_wait (pcpi_mul_wait),
.pcpi_ready(pcpi_mul_ready ) .pcpi_ready(pcpi_mul_ready)
); );
picorv32_pcpi_div pcpi_div ( picorv32_pcpi_div pcpi_div (
.clk (clk ), .clk (clk),
.resetn (resetn ), .resetn (resetn),
.pcpi_valid(pcpi_valid ), .pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ), .pcpi_insn (pcpi_insn),
.pcpi_rs1 (pcpi_rs1 ), .pcpi_rs1 (pcpi_rs1),
.pcpi_rs2 (pcpi_rs2 ), .pcpi_rs2 (pcpi_rs2),
.pcpi_wr (pcpi_div_wr ), .pcpi_wr (pcpi_div_wr),
.pcpi_rd (pcpi_div_rd ), .pcpi_rd (pcpi_div_rd),
.pcpi_wait (pcpi_div_wait ), .pcpi_wait (pcpi_div_wait),
.pcpi_ready(pcpi_div_ready ) .pcpi_ready(pcpi_div_ready)
); );
always @* begin always @* begin
@ -239,8 +241,7 @@ module picorv32 #(
if (!resetn) begin if (!resetn) begin
last_mem_valid <= 0; last_mem_valid <= 0;
end else begin end else begin
if (!last_mem_valid) if (!last_mem_valid) last_mem_valid <= mem_valid && !mem_ready;
last_mem_valid <= mem_valid && !mem_ready;
end end
end end
@ -256,7 +257,7 @@ module picorv32 #(
mem_la_wdata = {2{reg_op2[15:0]}}; mem_la_wdata = {2{reg_op2[15:0]}};
mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011; mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
case (reg_op1[1]) case (reg_op1[1])
1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]}; 1'b0: mem_rdata_word = {16'b0, mem_rdata[15:0]};
1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]}; 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
endcase endcase
end end
@ -264,8 +265,8 @@ module picorv32 #(
mem_la_wdata = {4{reg_op2[7:0]}}; mem_la_wdata = {4{reg_op2[7:0]}};
mem_la_wstrb = 4'b0001 << reg_op1[1:0]; mem_la_wstrb = 4'b0001 << reg_op1[1:0];
case (reg_op1[1:0]) case (reg_op1[1:0])
2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]}; 2'b00: mem_rdata_word = {24'b0, mem_rdata[7:0]};
2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]}; 2'b01: mem_rdata_word = {24'b0, mem_rdata[15:8]};
2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]}; 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]}; 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
endcase endcase
@ -301,10 +302,8 @@ module picorv32 #(
always @(posedge clk) begin always @(posedge clk) begin
if (!resetn || trap) begin if (!resetn || trap) begin
if (!resetn) if (!resetn) mem_state <= 0;
mem_state <= 0; if (!resetn || mem_ready) mem_valid <= 0;
if (!resetn || mem_ready)
mem_valid <= 0;
end else begin end else begin
if (mem_la_read || mem_la_write) begin if (mem_la_read || mem_la_write) begin
mem_addr <= mem_la_addr; mem_addr <= mem_la_addr;
@ -362,8 +361,27 @@ module picorv32 #(
reg instr_lui, instr_auipc, instr_jal, instr_jalr; reg instr_lui, instr_auipc, instr_jal, instr_jalr;
reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu; reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; reg
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; instr_addi,
instr_slti,
instr_sltiu,
instr_xori,
instr_ori,
instr_andi,
instr_slli,
instr_srli,
instr_srai;
reg
instr_add,
instr_sub,
instr_sll,
instr_slt,
instr_sltu,
instr_xor,
instr_srl,
instr_sra,
instr_or,
instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak; reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap; wire instr_trap;
@ -404,16 +422,16 @@ module picorv32 #(
reg [63:0] new_ascii_instr; reg [63:0] new_ascii_instr;
`FORMAL_KEEP reg [63:0] dbg_ascii_instr; reg [63:0] dbg_ascii_instr;
`FORMAL_KEEP reg [31:0] dbg_insn_imm; reg [31:0] dbg_insn_imm;
`FORMAL_KEEP reg [4:0] dbg_insn_rs1; reg [4:0] dbg_insn_rs1;
`FORMAL_KEEP reg [4:0] dbg_insn_rs2; reg [4:0] dbg_insn_rs2;
`FORMAL_KEEP reg [4:0] dbg_insn_rd; reg [4:0] dbg_insn_rd;
`FORMAL_KEEP reg [31:0] dbg_rs1val; reg [31:0] dbg_rs1val;
`FORMAL_KEEP reg [31:0] dbg_rs2val; reg [31:0] dbg_rs2val;
`FORMAL_KEEP reg dbg_rs1val_valid; reg dbg_rs1val_valid;
`FORMAL_KEEP reg dbg_rs2val_valid; reg dbg_rs2val_valid;
`FORMAL_KEEP reg [127:0] dbg_ascii_state; reg [127:0] dbg_ascii_state;
always @* begin always @* begin
new_ascii_instr = ""; new_ascii_instr = "";
@ -500,18 +518,14 @@ module picorv32 #(
q_insn_rd <= dbg_insn_rd; q_insn_rd <= dbg_insn_rd;
dbg_next <= launch_next_insn; dbg_next <= launch_next_insn;
if (!resetn || trap) if (!resetn || trap) dbg_valid_insn <= 0;
dbg_valid_insn <= 0; else if (launch_next_insn) dbg_valid_insn <= 1;
else if (launch_next_insn)
dbg_valid_insn <= 1;
if (decoder_trigger_q) begin if (decoder_trigger_q) begin
cached_ascii_instr <= new_ascii_instr; cached_ascii_instr <= new_ascii_instr;
cached_insn_imm <= decoded_imm; cached_insn_imm <= decoded_imm;
if (&next_insn_opcode[1:0]) if (&next_insn_opcode[1:0]) cached_insn_opcode <= next_insn_opcode;
cached_insn_opcode <= next_insn_opcode; else cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
else
cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
cached_insn_rs1 <= decoded_rs1; cached_insn_rs1 <= decoded_rs1;
cached_insn_rs2 <= decoded_rs2; cached_insn_rs2 <= decoded_rs2;
cached_insn_rd <= decoded_rd; cached_insn_rd <= decoded_rd;
@ -540,10 +554,8 @@ module picorv32 #(
dbg_insn_rd = cached_insn_rd; dbg_insn_rd = cached_insn_rd;
end else begin end else begin
dbg_ascii_instr = new_ascii_instr; dbg_ascii_instr = new_ascii_instr;
if (&next_insn_opcode[1:0]) if (&next_insn_opcode[1:0]) dbg_insn_opcode = next_insn_opcode;
dbg_insn_opcode = next_insn_opcode; else dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
else
dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
dbg_insn_imm = decoded_imm; dbg_insn_imm = decoded_imm;
dbg_insn_rs1 = decoded_rs1; dbg_insn_rs1 = decoded_rs1;
dbg_insn_rs2 = decoded_rs2; dbg_insn_rs2 = decoded_rs2;
@ -555,7 +567,8 @@ module picorv32 #(
`ifdef DEBUGASM `ifdef DEBUGASM
always @(posedge clk) begin always @(posedge clk) begin
if (dbg_next) begin if (dbg_next) begin
$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*"); $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode,
dbg_ascii_instr ? dbg_ascii_instr : "*");
end end
end end
`endif `endif
@ -564,9 +577,19 @@ module picorv32 #(
always @(posedge clk) begin always @(posedge clk) begin
if (dbg_next) begin if (dbg_next) begin
if (&dbg_insn_opcode[1:0]) if (&dbg_insn_opcode[1:0])
$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); $display(
"DECODE: 0x%08x 0x%08x %-0s",
dbg_insn_addr,
dbg_insn_opcode,
dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
);
else else
$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); $display(
"DECODE: 0x%08x 0x%04x %-0s",
dbg_insn_addr,
dbg_insn_opcode[15:0],
dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
);
end end
end end
`endif `endif
@ -593,7 +616,9 @@ module picorv32 #(
is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011; is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011; is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
{ decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0}); { decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed(
{mem_rdata_latched[31:12], 1'b0}
);
decoded_rd <= mem_rdata_latched[11:7]; decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[19:15]; decoded_rs1 <= mem_rdata_latched[19:15];
@ -690,18 +715,16 @@ module picorv32 #(
(* parallel_case *) (* parallel_case *)
case (1'b1) case (1'b1)
instr_jal: instr_jal: decoded_imm <= decoded_imm_j;
decoded_imm <= decoded_imm_j; |{instr_lui, instr_auipc} : decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_lui, instr_auipc}: |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm} :
decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
decoded_imm <= $signed(mem_rdata_q[31:20]); decoded_imm <= $signed(mem_rdata_q[31:20]);
is_beq_bne_blt_bge_bltu_bgeu: is_beq_bne_blt_bge_bltu_bgeu:
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}); decoded_imm <= $signed(
is_sb_sh_sw: {mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]}); );
default: is_sb_sh_sw: decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
decoded_imm <= 1'bx; default: decoded_imm <= 1'bx;
endcase endcase
end end
@ -794,14 +817,17 @@ module picorv32 #(
reg [31:0] alu_shl, alu_shr; reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts; reg alu_eq, alu_ltu, alu_lts;
generate if (TWO_CYCLE_ALU) begin generate
if (TWO_CYCLE_ALU) begin
always @(posedge clk) begin always @(posedge clk) begin
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq <= reg_op1 == reg_op2; alu_eq <= reg_op1 == reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2); alu_lts <= $signed(reg_op1) < $signed(reg_op2);
alu_ltu <= reg_op1 < reg_op2; alu_ltu <= reg_op1 < reg_op2;
alu_shl <= reg_op1 << reg_op2[4:0]; alu_shl <= reg_op1 << reg_op2[4:0];
alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; alu_shr <= $signed(
{instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}
) >>> reg_op2[4:0];
end end
end else begin end else begin
always @* begin always @* begin
@ -812,43 +838,33 @@ module picorv32 #(
alu_shl = reg_op1 << reg_op2[4:0]; alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end end
end endgenerate end
endgenerate
always @* begin always @* begin
alu_out_0 = 'bx; alu_out_0 = 'bx;
(* parallel_case, full_case *) (* parallel_case, full_case *)
case (1'b1) case (1'b1)
instr_beq: instr_beq: alu_out_0 = alu_eq;
alu_out_0 = alu_eq; instr_bne: alu_out_0 = !alu_eq;
instr_bne: instr_bge: alu_out_0 = !alu_lts;
alu_out_0 = !alu_eq; instr_bgeu: alu_out_0 = !alu_ltu;
instr_bge: is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
alu_out_0 = !alu_lts;
instr_bgeu:
alu_out_0 = !alu_ltu;
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_lts; alu_out_0 = alu_lts;
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
alu_out_0 = alu_ltu; alu_out_0 = alu_ltu;
endcase endcase
alu_out = 'bx; alu_out = 'bx;
(* parallel_case, full_case *) (* parallel_case, full_case *)
case (1'b1) case (1'b1)
is_lui_auipc_jal_jalr_addi_add_sub: is_lui_auipc_jal_jalr_addi_add_sub: alu_out = alu_add_sub;
alu_out = alu_add_sub; is_compare: alu_out = alu_out_0;
is_compare: instr_xori || instr_xor: alu_out = reg_op1 ^ reg_op2;
alu_out = alu_out_0; instr_ori || instr_or: alu_out = reg_op1 | reg_op2;
instr_xori || instr_xor: instr_andi || instr_and: alu_out = reg_op1 & reg_op2;
alu_out = reg_op1 ^ reg_op2; BARREL_SHIFTER && (instr_sll || instr_slli): alu_out = alu_shl;
instr_ori || instr_or: BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai): alu_out = alu_shr;
alu_out = reg_op1 | reg_op2;
instr_andi || instr_and:
alu_out = reg_op1 & reg_op2;
BARREL_SHIFTER && (instr_sll || instr_slli):
alu_out = alu_shl;
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
alu_out = alu_shr;
endcase endcase
end end
@ -885,8 +901,8 @@ module picorv32 #(
end end
end end
wire[31:0] cpuregs_rdata1; wire [31:0] cpuregs_rdata1;
wire[31:0] cpuregs_rdata2; wire [31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd; wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = decoded_rs1; wire [5:0] cpuregs_raddr1 = decoded_rs1;
@ -933,10 +949,8 @@ module picorv32 #(
end end
if (resetn && pcpi_valid && !pcpi_int_wait) begin if (resetn && pcpi_valid && !pcpi_int_wait) begin
if (pcpi_timeout_counter) if (pcpi_timeout_counter) pcpi_timeout_counter <= pcpi_timeout_counter - 1;
pcpi_timeout_counter <= pcpi_timeout_counter - 1; end else pcpi_timeout_counter <= ~0;
end else
pcpi_timeout_counter <= ~0;
pcpi_timeout <= !pcpi_timeout_counter; pcpi_timeout <= !pcpi_timeout_counter;
count_cycle <= resetn ? count_cycle + 1 : 0; count_cycle <= resetn ? count_cycle + 1 : 0;
next_irq_pending = irq_pending & LATCHED_IRQ; next_irq_pending = irq_pending & LATCHED_IRQ;
@ -953,8 +967,7 @@ module picorv32 #(
trace_valid <= 0; trace_valid <= 0;
if (!ENABLE_TRACE) if (!ENABLE_TRACE) trace_data <= 'bx;
trace_data <= 'bx;
if (!resetn) begin if (!resetn) begin
reg_pc <= PROGADDR_RESET; reg_pc <= PROGADDR_RESET;
@ -983,8 +996,7 @@ module picorv32 #(
end end
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end else
(* parallel_case, full_case *) (* parallel_case, full_case *) case (cpu_state)
case (cpu_state)
cpu_state_trap: begin cpu_state_trap: begin
trap <= 1; trap <= 1;
end end
@ -999,10 +1011,16 @@ module picorv32 #(
case (1'b1) case (1'b1)
latched_branch: begin latched_branch: begin
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc; current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);) `debug($display(
"ST_RD: %2d 0x%08x, BRANCH 0x%08x",
latched_rd,
reg_pc + (latched_compr ? 2 : 4),
current_pc
);)
end end
latched_store && !latched_branch: begin latched_store && !latched_branch: begin
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);) `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out
);)
end end
irq_state[0]: begin irq_state[0]: begin
current_pc = PROGADDR_IRQ; current_pc = PROGADDR_IRQ;
@ -1020,8 +1038,7 @@ module picorv32 #(
trace_valid <= 1; trace_valid <= 1;
if (latched_branch) if (latched_branch)
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe); trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
else else trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
end end
reg_pc <= current_pc; reg_pc <= current_pc;
@ -1037,27 +1054,21 @@ module picorv32 #(
latched_compr <= compressed_instr; latched_compr <= compressed_instr;
if (((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin if (((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
irq_state <= irq_state <= irq_state == 2'b00 ? 2'b01 : irq_state == 2'b01 ? 2'b10 : 2'b00;
irq_state == 2'b00 ? 2'b01 :
irq_state == 2'b01 ? 2'b10 : 2'b00;
latched_compr <= latched_compr; latched_compr <= latched_compr;
latched_rd <= irqregs_offset | irq_state[0]; latched_rd <= irqregs_offset | irq_state[0];
end else end else if ((decoder_trigger || do_waitirq) && instr_waitirq) begin
if ((decoder_trigger || do_waitirq) && instr_waitirq) begin
if (irq_pending) begin if (irq_pending) begin
latched_store <= 1; latched_store <= 1;
reg_out <= irq_pending; reg_out <= irq_pending;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
mem_do_rinst <= 1; mem_do_rinst <= 1;
end else end else do_waitirq <= 1;
do_waitirq <= 1; end else if (decoder_trigger) begin
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);) `debug($display("-- %-0t", $time);)
irq_delay <= irq_active; irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (ENABLE_TRACE) if (ENABLE_TRACE) latched_trace <= 1;
latched_trace <= 1;
count_instr <= count_instr + 1; count_instr <= count_instr + 1;
if (instr_jal) begin if (instr_jal) begin
mem_do_rinst <= 1; mem_do_rinst <= 1;
@ -1094,28 +1105,22 @@ module picorv32 #(
reg_out <= pcpi_int_rd; reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr; latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end else if (pcpi_timeout || instr_ecall_ebreak) begin
if (pcpi_timeout || instr_ecall_ebreak) begin
pcpi_valid <= 0; pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (!irq_mask[irq_ebreak] && !irq_active) begin if (!irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1; next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end else cpu_state <= cpu_state_trap;
cpu_state <= cpu_state_trap;
end end
end end
is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *) (* parallel_case, full_case *)
case (1'b1) case (1'b1)
instr_rdcycle: instr_rdcycle: reg_out <= count_cycle[31:0];
reg_out <= count_cycle[31:0]; instr_rdcycleh: reg_out <= count_cycle[63:32];
instr_rdcycleh: instr_rdinstr: reg_out <= count_instr[31:0];
reg_out <= count_cycle[63:32]; instr_rdinstrh: reg_out <= count_instr[63:32];
instr_rdinstr:
reg_out <= count_instr[31:0];
instr_rdinstrh:
reg_out <= count_instr[63:32];
endcase endcase
latched_store <= 1; latched_store <= 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
@ -1123,10 +1128,8 @@ module picorv32 #(
is_lui_auipc_jal: begin is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc; reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm; reg_op2 <= decoded_imm;
if (TWO_CYCLE_ALU) if (TWO_CYCLE_ALU) alu_wait <= 1;
alu_wait <= 1; else mem_do_rinst <= mem_do_prefetch;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
instr_getq: begin instr_getq: begin
@ -1152,7 +1155,7 @@ module picorv32 #(
latched_branch <= 1; latched_branch <= 1;
latched_store <= 1; latched_store <= 1;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1 & 32'h fffffffe; reg_out <= cpuregs_rs1 & 32'hfffffffe;
dbg_rs1val <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1; dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
@ -1197,10 +1200,8 @@ module picorv32 #(
dbg_rs1val <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1; dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm; reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
if (TWO_CYCLE_ALU) if (TWO_CYCLE_ALU) alu_wait <= 1;
alu_wait <= 1; else mem_do_rinst <= mem_do_prefetch;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
default: begin default: begin
@ -1226,8 +1227,7 @@ module picorv32 #(
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1; alu_wait <= 1;
end else end else mem_do_rinst <= mem_do_prefetch;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
endcase endcase
@ -1252,15 +1252,13 @@ module picorv32 #(
reg_out <= pcpi_int_rd; reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr; latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end else if (pcpi_timeout || instr_ecall_ebreak) begin
if (pcpi_timeout || instr_ecall_ebreak) begin
pcpi_valid <= 0; pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (!irq_mask[irq_ebreak] && !irq_active) begin if (!irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1; next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end else cpu_state <= cpu_state_trap;
cpu_state <= cpu_state_trap;
end end
end end
is_sb_sh_sw: begin is_sb_sh_sw: begin
@ -1274,8 +1272,7 @@ module picorv32 #(
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1; alu_wait <= 1;
end else end else mem_do_rinst <= mem_do_prefetch;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
endcase endcase
@ -1286,13 +1283,11 @@ module picorv32 #(
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2; mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2; alu_wait <= alu_wait_2;
end else end else if (is_beq_bne_blt_bge_bltu_bgeu) begin
if (is_beq_bne_blt_bge_bltu_bgeu) begin
latched_rd <= 0; latched_rd <= 0;
latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
if (mem_done) if (mem_done) cpu_state <= cpu_state_fetch;
cpu_state <= cpu_state_fetch;
if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
decoder_trigger <= 0; decoder_trigger <= 0;
set_mem_do_rinst = 1; set_mem_do_rinst = 1;
@ -1331,8 +1326,7 @@ module picorv32 #(
end end
cpu_state_stmem: begin cpu_state_stmem: begin
if (ENABLE_TRACE) if (ENABLE_TRACE) reg_out <= reg_op2;
reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin if (!mem_do_wdata) begin
(* parallel_case, full_case *) (* parallel_case, full_case *)
@ -1392,32 +1386,27 @@ module picorv32 #(
endcase endcase
next_irq_pending = next_irq_pending | irq; next_irq_pending = next_irq_pending | irq;
if(timer) if (timer) if (timer - 1 == 0) next_irq_pending[irq_timer] = 1;
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
if (resetn && (mem_do_rdata || mem_do_wdata)) begin if (resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
if (!irq_mask[irq_buserror] && !irq_active) begin if (!irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1; next_irq_pending[irq_buserror] = 1;
end else end else cpu_state <= cpu_state_trap;
cpu_state <= cpu_state_trap;
end end
if (mem_wordsize == 1 && reg_op1[0] != 0) begin if (mem_wordsize == 1 && reg_op1[0] != 0) begin
`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);) `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
if (!irq_mask[irq_buserror] && !irq_active) begin if (!irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1; next_irq_pending[irq_buserror] = 1;
end else end else cpu_state <= cpu_state_trap;
cpu_state <= cpu_state_trap;
end end
end end
if (resetn && mem_do_rinst && (|reg_pc[1:0])) begin if (resetn && mem_do_rinst && (|reg_pc[1:0])) begin
`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);) `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
if (!irq_mask[irq_buserror] && !irq_active) begin if (!irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1; next_irq_pending[irq_buserror] = 1;
end else end else cpu_state <= cpu_state_trap;
cpu_state <= cpu_state_trap;
end end
if (!resetn || mem_done) begin if (!resetn || mem_done) begin
@ -1427,12 +1416,9 @@ module picorv32 #(
mem_do_wdata <= 0; mem_do_wdata <= 0;
end end
if (set_mem_do_rinst) if (set_mem_do_rinst) mem_do_rinst <= 1;
mem_do_rinst <= 1; if (set_mem_do_rdata) mem_do_rdata <= 1;
if (set_mem_do_rdata) if (set_mem_do_wdata) mem_do_wdata <= 1;
mem_do_rdata <= 1;
if (set_mem_do_wdata)
mem_do_wdata <= 1;
irq_pending <= next_irq_pending & ~MASKED_IRQ; irq_pending <= next_irq_pending & ~MASKED_IRQ;
current_pc = 'bx; current_pc = 'bx;
@ -1440,7 +1426,8 @@ module picorv32 #(
endmodule endmodule
module picorv32_regs ( module picorv32_regs (
input clk, wen, input clk,
wen,
input [5:0] waddr, input [5:0] waddr,
input [5:0] raddr1, input [5:0] raddr1,
input [5:0] raddr2, input [5:0] raddr2,
@ -1448,9 +1435,8 @@ module picorv32_regs (
output [31:0] rdata1, output [31:0] rdata1,
output [31:0] rdata2 output [31:0] rdata2
); );
reg [31:0] regs [0:35]; reg [31:0] regs[0:35];
always @(posedge clk) always @(posedge clk) if (wen) regs[waddr[5:0]] <= wdata;
if (wen) regs[waddr[5:0]] <= wdata;
assign rdata1 = regs[raddr1]; assign rdata1 = regs[raddr1];
assign rdata2 = regs[raddr2]; assign rdata2 = regs[raddr2];
endmodule endmodule
@ -1463,7 +1449,8 @@ module picorv32_pcpi_mul #(
parameter STEPS_AT_ONCE = 1, parameter STEPS_AT_ONCE = 1,
parameter CARRY_CHAIN = 4 parameter CARRY_CHAIN = 4
) ( ) (
input clk, resetn, input clk,
resetn,
input pcpi_valid, input pcpi_valid,
input [31:0] pcpi_insn, input [31:0] pcpi_insn,
@ -1517,7 +1504,7 @@ module picorv32_pcpi_mul #(
next_rs1 = rs1; next_rs1 = rs1;
next_rs2 = rs2; next_rs2 = rs2;
for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin for (i = 0; i < STEPS_AT_ONCE; i = i + 1) begin
this_rs2 = next_rs1[0] ? next_rs2 : 0; this_rs2 = next_rs1[0] ? next_rs2 : 0;
if (CARRY_CHAIN == 0) begin if (CARRY_CHAIN == 0) begin
next_rdt = next_rd ^ next_rdx ^ this_rs2; next_rdt = next_rd ^ next_rdx ^ this_rs2;
@ -1539,17 +1526,12 @@ module picorv32_pcpi_mul #(
mul_finish <= 0; mul_finish <= 0;
if (!resetn) begin if (!resetn) begin
mul_waiting <= 1; mul_waiting <= 1;
end else end else if (mul_waiting) begin
if (mul_waiting) begin if (instr_rs1_signed) rs1 <= $signed(pcpi_rs1);
if (instr_rs1_signed) else rs1 <= $unsigned(pcpi_rs1);
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed) if (instr_rs2_signed) rs2 <= $signed(pcpi_rs2);
rs2 <= $signed(pcpi_rs2); else rs2 <= $unsigned(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
rd <= 0; rd <= 0;
rdx <= 0; rdx <= 0;
@ -1585,7 +1567,8 @@ endmodule
***************************************************************/ ***************************************************************/
module picorv32_pcpi_div ( module picorv32_pcpi_div (
input clk, resetn, input clk,
resetn,
input pcpi_valid, input pcpi_valid,
input [31:0] pcpi_insn, input [31:0] pcpi_insn,
@ -1635,24 +1618,20 @@ module picorv32_pcpi_div (
if (!resetn) begin if (!resetn) begin
running <= 0; running <= 0;
end else end else if (start) begin
if (start) begin
running <= 1; running <= 1;
dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1; dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31; divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]); outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
quotient <= 0; quotient <= 0;
quotient_msk <= 1 << 31; quotient_msk <= 1 << 31;
end else end else if (!quotient_msk && running) begin
if (!quotient_msk && running) begin
running <= 0; running <= 0;
pcpi_ready <= 1; pcpi_ready <= 1;
pcpi_wr <= 1; pcpi_wr <= 1;
if (instr_div || instr_divu) if (instr_div || instr_divu) pcpi_rd <= outsign ? -quotient : quotient;
pcpi_rd <= outsign ? -quotient : quotient; else pcpi_rd <= outsign ? -dividend : dividend;
else
pcpi_rd <= outsign ? -dividend : dividend;
end else begin end else begin
if (divisor <= dividend) begin if (divisor <= dividend) begin