Format code.
This commit is contained in:
colin.liang
parent
665f26dc63
commit
4beed17d0a
403
picorv32.v
403
picorv32.v
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@ -30,9 +30,9 @@
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// `define DEBUG
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`ifdef DEBUG
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`define debug(debug_command) debug_command
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`define debug(debug_command) debug_command
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`else
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`define debug(debug_command)
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`define debug(debug_command)
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`endif
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`define assert(assert_expr) empty_statement
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@ -43,18 +43,19 @@
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***************************************************************/
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module picorv32 #(
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] BARREL_SHIFTER = 0,
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parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
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parameter [ 0:0] TWO_CYCLE_ALU = 0,
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parameter [ 0:0] ENABLE_TRACE = 0,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
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parameter [31:0] STACKADDR = 32'h ffff_ffff
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parameter [0:0] TWO_STAGE_SHIFT = 1,
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parameter [0:0] BARREL_SHIFTER = 0,
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parameter [0:0] TWO_CYCLE_COMPARE = 0,
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parameter [0:0] TWO_CYCLE_ALU = 0,
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parameter [0:0] ENABLE_TRACE = 0,
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parameter [31:0] MASKED_IRQ = 32'h0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'hffff_ffff,
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parameter [31:0] PROGADDR_RESET = 32'h0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h0000_0010,
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parameter [31:0] STACKADDR = 32'hffff_ffff
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) (
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input clk, resetn,
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input clk,
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resetn,
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output reg trap,
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output reg mem_valid,
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@ -98,9 +99,9 @@ module picorv32 #(
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localparam integer irqregs_offset = 32;
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localparam integer regfile_size = 32 + 4;
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localparam integer regindex_bits = 5 + 1;
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localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
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localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
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localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
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localparam [35:0] TRACE_BRANCH = {4'b0001, 32'b0};
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localparam [35:0] TRACE_ADDR = {4'b0010, 32'b0};
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localparam [35:0] TRACE_IRQ = {4'b1000, 32'b0};
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reg [63:0] count_cycle, count_instr;
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reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
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@ -115,7 +116,7 @@ module picorv32 #(
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wire dbg_mem_ready = mem_ready;
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wire [31:0] dbg_mem_addr = mem_addr;
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wire [31:0] dbg_mem_wdata = mem_wdata;
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wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
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wire [3:0] dbg_mem_wstrb = mem_wstrb;
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wire [31:0] dbg_mem_rdata = mem_rdata;
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assign pcpi_rs1 = reg_op1;
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@ -132,7 +133,8 @@ module picorv32 #(
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task empty_statement;
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// This task is used by the `assert directive in non-formal mode to
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// avoid empty statement (which are unsupported by plain Verilog syntax).
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begin end
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begin
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end
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endtask
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// Internal PCPI Cores
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@ -154,29 +156,29 @@ module picorv32 #(
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picorv32_pcpi_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_valid(pcpi_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_mul_wr ),
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.pcpi_rd (pcpi_mul_rd ),
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.pcpi_wait (pcpi_mul_wait ),
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.pcpi_ready(pcpi_mul_ready )
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.clk (clk),
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.resetn (resetn),
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.pcpi_valid(pcpi_valid),
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.pcpi_insn (pcpi_insn),
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.pcpi_rs1 (pcpi_rs1),
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.pcpi_rs2 (pcpi_rs2),
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.pcpi_wr (pcpi_mul_wr),
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.pcpi_rd (pcpi_mul_rd),
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.pcpi_wait (pcpi_mul_wait),
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.pcpi_ready(pcpi_mul_ready)
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);
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picorv32_pcpi_div pcpi_div (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_valid(pcpi_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_div_wr ),
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.pcpi_rd (pcpi_div_rd ),
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.pcpi_wait (pcpi_div_wait ),
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.pcpi_ready(pcpi_div_ready )
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.clk (clk),
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.resetn (resetn),
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.pcpi_valid(pcpi_valid),
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.pcpi_insn (pcpi_insn),
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.pcpi_rs1 (pcpi_rs1),
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.pcpi_rs2 (pcpi_rs2),
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.pcpi_wr (pcpi_div_wr),
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.pcpi_rd (pcpi_div_rd),
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.pcpi_wait (pcpi_div_wait),
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.pcpi_ready(pcpi_div_ready)
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);
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always @* begin
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@ -239,8 +241,7 @@ module picorv32 #(
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if (!resetn) begin
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last_mem_valid <= 0;
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end else begin
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if (!last_mem_valid)
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last_mem_valid <= mem_valid && !mem_ready;
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if (!last_mem_valid) last_mem_valid <= mem_valid && !mem_ready;
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end
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end
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@ -256,7 +257,7 @@ module picorv32 #(
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mem_la_wdata = {2{reg_op2[15:0]}};
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mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
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case (reg_op1[1])
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1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
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1'b0: mem_rdata_word = {16'b0, mem_rdata[15:0]};
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1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
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endcase
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end
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@ -264,8 +265,8 @@ module picorv32 #(
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mem_la_wdata = {4{reg_op2[7:0]}};
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mem_la_wstrb = 4'b0001 << reg_op1[1:0];
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case (reg_op1[1:0])
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2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
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2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
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2'b00: mem_rdata_word = {24'b0, mem_rdata[7:0]};
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2'b01: mem_rdata_word = {24'b0, mem_rdata[15:8]};
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2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
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2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
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endcase
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@ -301,10 +302,8 @@ module picorv32 #(
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always @(posedge clk) begin
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if (!resetn || trap) begin
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if (!resetn)
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mem_state <= 0;
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if (!resetn || mem_ready)
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mem_valid <= 0;
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if (!resetn) mem_state <= 0;
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if (!resetn || mem_ready) mem_valid <= 0;
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end else begin
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if (mem_la_read || mem_la_write) begin
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mem_addr <= mem_la_addr;
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@ -362,8 +361,27 @@ module picorv32 #(
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reg instr_lui, instr_auipc, instr_jal, instr_jalr;
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reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
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reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
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reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
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reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
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reg
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instr_addi,
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instr_slti,
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instr_sltiu,
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instr_xori,
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instr_ori,
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instr_andi,
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instr_slli,
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instr_srli,
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instr_srai;
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reg
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instr_add,
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instr_sub,
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instr_sll,
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instr_slt,
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instr_sltu,
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instr_xor,
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instr_srl,
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instr_sra,
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instr_or,
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instr_and;
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reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
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reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
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wire instr_trap;
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@ -404,16 +422,16 @@ module picorv32 #(
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reg [63:0] new_ascii_instr;
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`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
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`FORMAL_KEEP reg [31:0] dbg_insn_imm;
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`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
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`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
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`FORMAL_KEEP reg [4:0] dbg_insn_rd;
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`FORMAL_KEEP reg [31:0] dbg_rs1val;
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`FORMAL_KEEP reg [31:0] dbg_rs2val;
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`FORMAL_KEEP reg dbg_rs1val_valid;
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`FORMAL_KEEP reg dbg_rs2val_valid;
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`FORMAL_KEEP reg [127:0] dbg_ascii_state;
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reg [63:0] dbg_ascii_instr;
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reg [31:0] dbg_insn_imm;
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reg [4:0] dbg_insn_rs1;
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reg [4:0] dbg_insn_rs2;
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reg [4:0] dbg_insn_rd;
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reg [31:0] dbg_rs1val;
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reg [31:0] dbg_rs2val;
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reg dbg_rs1val_valid;
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reg dbg_rs2val_valid;
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reg [127:0] dbg_ascii_state;
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always @* begin
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new_ascii_instr = "";
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@ -500,18 +518,14 @@ module picorv32 #(
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q_insn_rd <= dbg_insn_rd;
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dbg_next <= launch_next_insn;
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if (!resetn || trap)
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dbg_valid_insn <= 0;
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else if (launch_next_insn)
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dbg_valid_insn <= 1;
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if (!resetn || trap) dbg_valid_insn <= 0;
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else if (launch_next_insn) dbg_valid_insn <= 1;
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if (decoder_trigger_q) begin
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cached_ascii_instr <= new_ascii_instr;
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cached_insn_imm <= decoded_imm;
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if (&next_insn_opcode[1:0])
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cached_insn_opcode <= next_insn_opcode;
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else
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cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
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if (&next_insn_opcode[1:0]) cached_insn_opcode <= next_insn_opcode;
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else cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
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cached_insn_rs1 <= decoded_rs1;
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cached_insn_rs2 <= decoded_rs2;
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cached_insn_rd <= decoded_rd;
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@ -540,10 +554,8 @@ module picorv32 #(
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dbg_insn_rd = cached_insn_rd;
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end else begin
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dbg_ascii_instr = new_ascii_instr;
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if (&next_insn_opcode[1:0])
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dbg_insn_opcode = next_insn_opcode;
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else
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dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
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if (&next_insn_opcode[1:0]) dbg_insn_opcode = next_insn_opcode;
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else dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
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dbg_insn_imm = decoded_imm;
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dbg_insn_rs1 = decoded_rs1;
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dbg_insn_rs2 = decoded_rs2;
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@ -555,7 +567,8 @@ module picorv32 #(
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`ifdef DEBUGASM
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always @(posedge clk) begin
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if (dbg_next) begin
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$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
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$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode,
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dbg_ascii_instr ? dbg_ascii_instr : "*");
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end
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end
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`endif
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@ -564,9 +577,19 @@ module picorv32 #(
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always @(posedge clk) begin
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if (dbg_next) begin
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if (&dbg_insn_opcode[1:0])
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$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
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$display(
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"DECODE: 0x%08x 0x%08x %-0s",
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dbg_insn_addr,
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dbg_insn_opcode,
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dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
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);
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else
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$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
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$display(
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"DECODE: 0x%08x 0x%04x %-0s",
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dbg_insn_addr,
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dbg_insn_opcode[15:0],
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dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
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);
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end
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end
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`endif
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@ -593,7 +616,9 @@ module picorv32 #(
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is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
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is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
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{ decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
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{ decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed(
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{mem_rdata_latched[31:12], 1'b0}
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);
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decoded_rd <= mem_rdata_latched[11:7];
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decoded_rs1 <= mem_rdata_latched[19:15];
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@ -690,18 +715,16 @@ module picorv32 #(
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(* parallel_case *)
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case (1'b1)
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instr_jal:
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decoded_imm <= decoded_imm_j;
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|{instr_lui, instr_auipc}:
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decoded_imm <= mem_rdata_q[31:12] << 12;
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|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
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instr_jal: decoded_imm <= decoded_imm_j;
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|{instr_lui, instr_auipc} : decoded_imm <= mem_rdata_q[31:12] << 12;
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|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm} :
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decoded_imm <= $signed(mem_rdata_q[31:20]);
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is_beq_bne_blt_bge_bltu_bgeu:
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decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
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is_sb_sh_sw:
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decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
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default:
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decoded_imm <= 1'bx;
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decoded_imm <= $signed(
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{mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}
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);
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is_sb_sh_sw: decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
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default: decoded_imm <= 1'bx;
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endcase
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end
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@ -794,14 +817,17 @@ module picorv32 #(
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reg [31:0] alu_shl, alu_shr;
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reg alu_eq, alu_ltu, alu_lts;
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generate if (TWO_CYCLE_ALU) begin
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generate
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if (TWO_CYCLE_ALU) begin
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always @(posedge clk) begin
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alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
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alu_eq <= reg_op1 == reg_op2;
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alu_lts <= $signed(reg_op1) < $signed(reg_op2);
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alu_ltu <= reg_op1 < reg_op2;
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alu_shl <= reg_op1 << reg_op2[4:0];
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alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
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alu_shr <= $signed(
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{instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}
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) >>> reg_op2[4:0];
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end
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end else begin
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always @* begin
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@ -812,43 +838,33 @@ module picorv32 #(
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alu_shl = reg_op1 << reg_op2[4:0];
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alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
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end
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end endgenerate
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end
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endgenerate
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always @* begin
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alu_out_0 = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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instr_beq:
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alu_out_0 = alu_eq;
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instr_bne:
|
||||
alu_out_0 = !alu_eq;
|
||||
instr_bge:
|
||||
alu_out_0 = !alu_lts;
|
||||
instr_bgeu:
|
||||
alu_out_0 = !alu_ltu;
|
||||
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
|
||||
instr_beq: alu_out_0 = alu_eq;
|
||||
instr_bne: alu_out_0 = !alu_eq;
|
||||
instr_bge: alu_out_0 = !alu_lts;
|
||||
instr_bgeu: alu_out_0 = !alu_ltu;
|
||||
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
|
||||
alu_out_0 = alu_lts;
|
||||
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
|
||||
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
|
||||
alu_out_0 = alu_ltu;
|
||||
endcase
|
||||
|
||||
alu_out = 'bx;
|
||||
(* parallel_case, full_case *)
|
||||
case (1'b1)
|
||||
is_lui_auipc_jal_jalr_addi_add_sub:
|
||||
alu_out = alu_add_sub;
|
||||
is_compare:
|
||||
alu_out = alu_out_0;
|
||||
instr_xori || instr_xor:
|
||||
alu_out = reg_op1 ^ reg_op2;
|
||||
instr_ori || instr_or:
|
||||
alu_out = reg_op1 | reg_op2;
|
||||
instr_andi || instr_and:
|
||||
alu_out = reg_op1 & reg_op2;
|
||||
BARREL_SHIFTER && (instr_sll || instr_slli):
|
||||
alu_out = alu_shl;
|
||||
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
|
||||
alu_out = alu_shr;
|
||||
is_lui_auipc_jal_jalr_addi_add_sub: alu_out = alu_add_sub;
|
||||
is_compare: alu_out = alu_out_0;
|
||||
instr_xori || instr_xor: alu_out = reg_op1 ^ reg_op2;
|
||||
instr_ori || instr_or: alu_out = reg_op1 | reg_op2;
|
||||
instr_andi || instr_and: alu_out = reg_op1 & reg_op2;
|
||||
BARREL_SHIFTER && (instr_sll || instr_slli): alu_out = alu_shl;
|
||||
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai): alu_out = alu_shr;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
|
@ -885,8 +901,8 @@ module picorv32 #(
|
|||
end
|
||||
end
|
||||
|
||||
wire[31:0] cpuregs_rdata1;
|
||||
wire[31:0] cpuregs_rdata2;
|
||||
wire [31:0] cpuregs_rdata1;
|
||||
wire [31:0] cpuregs_rdata2;
|
||||
|
||||
wire [5:0] cpuregs_waddr = latched_rd;
|
||||
wire [5:0] cpuregs_raddr1 = decoded_rs1;
|
||||
|
|
@ -933,10 +949,8 @@ module picorv32 #(
|
|||
end
|
||||
|
||||
if (resetn && pcpi_valid && !pcpi_int_wait) begin
|
||||
if (pcpi_timeout_counter)
|
||||
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
|
||||
end else
|
||||
pcpi_timeout_counter <= ~0;
|
||||
if (pcpi_timeout_counter) pcpi_timeout_counter <= pcpi_timeout_counter - 1;
|
||||
end else pcpi_timeout_counter <= ~0;
|
||||
pcpi_timeout <= !pcpi_timeout_counter;
|
||||
count_cycle <= resetn ? count_cycle + 1 : 0;
|
||||
next_irq_pending = irq_pending & LATCHED_IRQ;
|
||||
|
|
@ -953,8 +967,7 @@ module picorv32 #(
|
|||
|
||||
trace_valid <= 0;
|
||||
|
||||
if (!ENABLE_TRACE)
|
||||
trace_data <= 'bx;
|
||||
if (!ENABLE_TRACE) trace_data <= 'bx;
|
||||
|
||||
if (!resetn) begin
|
||||
reg_pc <= PROGADDR_RESET;
|
||||
|
|
@ -983,8 +996,7 @@ module picorv32 #(
|
|||
end
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else
|
||||
(* parallel_case, full_case *)
|
||||
case (cpu_state)
|
||||
(* parallel_case, full_case *) case (cpu_state)
|
||||
cpu_state_trap: begin
|
||||
trap <= 1;
|
||||
end
|
||||
|
|
@ -999,10 +1011,16 @@ module picorv32 #(
|
|||
case (1'b1)
|
||||
latched_branch: begin
|
||||
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
|
||||
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
|
||||
`debug($display(
|
||||
"ST_RD: %2d 0x%08x, BRANCH 0x%08x",
|
||||
latched_rd,
|
||||
reg_pc + (latched_compr ? 2 : 4),
|
||||
current_pc
|
||||
);)
|
||||
end
|
||||
latched_store && !latched_branch: begin
|
||||
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
|
||||
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out
|
||||
);)
|
||||
end
|
||||
irq_state[0]: begin
|
||||
current_pc = PROGADDR_IRQ;
|
||||
|
|
@ -1020,8 +1038,7 @@ module picorv32 #(
|
|||
trace_valid <= 1;
|
||||
if (latched_branch)
|
||||
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
|
||||
else
|
||||
trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
|
||||
else trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
|
||||
end
|
||||
|
||||
reg_pc <= current_pc;
|
||||
|
|
@ -1037,27 +1054,21 @@ module picorv32 #(
|
|||
latched_compr <= compressed_instr;
|
||||
|
||||
if (((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
|
||||
irq_state <=
|
||||
irq_state == 2'b00 ? 2'b01 :
|
||||
irq_state == 2'b01 ? 2'b10 : 2'b00;
|
||||
irq_state <= irq_state == 2'b00 ? 2'b01 : irq_state == 2'b01 ? 2'b10 : 2'b00;
|
||||
latched_compr <= latched_compr;
|
||||
latched_rd <= irqregs_offset | irq_state[0];
|
||||
end else
|
||||
if ((decoder_trigger || do_waitirq) && instr_waitirq) begin
|
||||
end else if ((decoder_trigger || do_waitirq) && instr_waitirq) begin
|
||||
if (irq_pending) begin
|
||||
latched_store <= 1;
|
||||
reg_out <= irq_pending;
|
||||
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
|
||||
mem_do_rinst <= 1;
|
||||
end else
|
||||
do_waitirq <= 1;
|
||||
end else
|
||||
if (decoder_trigger) begin
|
||||
end else do_waitirq <= 1;
|
||||
end else if (decoder_trigger) begin
|
||||
`debug($display("-- %-0t", $time);)
|
||||
irq_delay <= irq_active;
|
||||
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
|
||||
if (ENABLE_TRACE)
|
||||
latched_trace <= 1;
|
||||
if (ENABLE_TRACE) latched_trace <= 1;
|
||||
count_instr <= count_instr + 1;
|
||||
if (instr_jal) begin
|
||||
mem_do_rinst <= 1;
|
||||
|
|
@ -1094,28 +1105,22 @@ module picorv32 #(
|
|||
reg_out <= pcpi_int_rd;
|
||||
latched_store <= pcpi_int_wr;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else
|
||||
if (pcpi_timeout || instr_ecall_ebreak) begin
|
||||
end else if (pcpi_timeout || instr_ecall_ebreak) begin
|
||||
pcpi_valid <= 0;
|
||||
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
|
||||
if (!irq_mask[irq_ebreak] && !irq_active) begin
|
||||
next_irq_pending[irq_ebreak] = 1;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end else cpu_state <= cpu_state_trap;
|
||||
end
|
||||
end
|
||||
is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
|
||||
(* parallel_case, full_case *)
|
||||
case (1'b1)
|
||||
instr_rdcycle:
|
||||
reg_out <= count_cycle[31:0];
|
||||
instr_rdcycleh:
|
||||
reg_out <= count_cycle[63:32];
|
||||
instr_rdinstr:
|
||||
reg_out <= count_instr[31:0];
|
||||
instr_rdinstrh:
|
||||
reg_out <= count_instr[63:32];
|
||||
instr_rdcycle: reg_out <= count_cycle[31:0];
|
||||
instr_rdcycleh: reg_out <= count_cycle[63:32];
|
||||
instr_rdinstr: reg_out <= count_instr[31:0];
|
||||
instr_rdinstrh: reg_out <= count_instr[63:32];
|
||||
endcase
|
||||
latched_store <= 1;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
|
|
@ -1123,10 +1128,8 @@ module picorv32 #(
|
|||
is_lui_auipc_jal: begin
|
||||
reg_op1 <= instr_lui ? 0 : reg_pc;
|
||||
reg_op2 <= decoded_imm;
|
||||
if (TWO_CYCLE_ALU)
|
||||
alu_wait <= 1;
|
||||
else
|
||||
mem_do_rinst <= mem_do_prefetch;
|
||||
if (TWO_CYCLE_ALU) alu_wait <= 1;
|
||||
else mem_do_rinst <= mem_do_prefetch;
|
||||
cpu_state <= cpu_state_exec;
|
||||
end
|
||||
instr_getq: begin
|
||||
|
|
@ -1152,7 +1155,7 @@ module picorv32 #(
|
|||
latched_branch <= 1;
|
||||
latched_store <= 1;
|
||||
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
|
||||
reg_out <= cpuregs_rs1 & 32'h fffffffe;
|
||||
reg_out <= cpuregs_rs1 & 32'hfffffffe;
|
||||
dbg_rs1val <= cpuregs_rs1;
|
||||
dbg_rs1val_valid <= 1;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
|
|
@ -1197,10 +1200,8 @@ module picorv32 #(
|
|||
dbg_rs1val <= cpuregs_rs1;
|
||||
dbg_rs1val_valid <= 1;
|
||||
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
|
||||
if (TWO_CYCLE_ALU)
|
||||
alu_wait <= 1;
|
||||
else
|
||||
mem_do_rinst <= mem_do_prefetch;
|
||||
if (TWO_CYCLE_ALU) alu_wait <= 1;
|
||||
else mem_do_rinst <= mem_do_prefetch;
|
||||
cpu_state <= cpu_state_exec;
|
||||
end
|
||||
default: begin
|
||||
|
|
@ -1226,8 +1227,7 @@ module picorv32 #(
|
|||
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
|
||||
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
|
||||
alu_wait <= 1;
|
||||
end else
|
||||
mem_do_rinst <= mem_do_prefetch;
|
||||
end else mem_do_rinst <= mem_do_prefetch;
|
||||
cpu_state <= cpu_state_exec;
|
||||
end
|
||||
endcase
|
||||
|
|
@ -1252,15 +1252,13 @@ module picorv32 #(
|
|||
reg_out <= pcpi_int_rd;
|
||||
latched_store <= pcpi_int_wr;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else
|
||||
if (pcpi_timeout || instr_ecall_ebreak) begin
|
||||
end else if (pcpi_timeout || instr_ecall_ebreak) begin
|
||||
pcpi_valid <= 0;
|
||||
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
|
||||
if (!irq_mask[irq_ebreak] && !irq_active) begin
|
||||
next_irq_pending[irq_ebreak] = 1;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end else cpu_state <= cpu_state_trap;
|
||||
end
|
||||
end
|
||||
is_sb_sh_sw: begin
|
||||
|
|
@ -1274,8 +1272,7 @@ module picorv32 #(
|
|||
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
|
||||
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
|
||||
alu_wait <= 1;
|
||||
end else
|
||||
mem_do_rinst <= mem_do_prefetch;
|
||||
end else mem_do_rinst <= mem_do_prefetch;
|
||||
cpu_state <= cpu_state_exec;
|
||||
end
|
||||
endcase
|
||||
|
|
@ -1286,13 +1283,11 @@ module picorv32 #(
|
|||
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
|
||||
mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
|
||||
alu_wait <= alu_wait_2;
|
||||
end else
|
||||
if (is_beq_bne_blt_bge_bltu_bgeu) begin
|
||||
end else if (is_beq_bne_blt_bge_bltu_bgeu) begin
|
||||
latched_rd <= 0;
|
||||
latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
|
||||
latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
|
||||
if (mem_done)
|
||||
cpu_state <= cpu_state_fetch;
|
||||
if (mem_done) cpu_state <= cpu_state_fetch;
|
||||
if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
|
||||
decoder_trigger <= 0;
|
||||
set_mem_do_rinst = 1;
|
||||
|
|
@ -1331,8 +1326,7 @@ module picorv32 #(
|
|||
end
|
||||
|
||||
cpu_state_stmem: begin
|
||||
if (ENABLE_TRACE)
|
||||
reg_out <= reg_op2;
|
||||
if (ENABLE_TRACE) reg_out <= reg_op2;
|
||||
if (!mem_do_prefetch || mem_done) begin
|
||||
if (!mem_do_wdata) begin
|
||||
(* parallel_case, full_case *)
|
||||
|
|
@ -1392,32 +1386,27 @@ module picorv32 #(
|
|||
endcase
|
||||
|
||||
next_irq_pending = next_irq_pending | irq;
|
||||
if(timer)
|
||||
if (timer - 1 == 0)
|
||||
next_irq_pending[irq_timer] = 1;
|
||||
if (timer) if (timer - 1 == 0) next_irq_pending[irq_timer] = 1;
|
||||
|
||||
if (resetn && (mem_do_rdata || mem_do_wdata)) begin
|
||||
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
|
||||
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
|
||||
if (!irq_mask[irq_buserror] && !irq_active) begin
|
||||
next_irq_pending[irq_buserror] = 1;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end else cpu_state <= cpu_state_trap;
|
||||
end
|
||||
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
|
||||
`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
|
||||
if (!irq_mask[irq_buserror] && !irq_active) begin
|
||||
next_irq_pending[irq_buserror] = 1;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end else cpu_state <= cpu_state_trap;
|
||||
end
|
||||
end
|
||||
if (resetn && mem_do_rinst && (|reg_pc[1:0])) begin
|
||||
`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
|
||||
if (!irq_mask[irq_buserror] && !irq_active) begin
|
||||
next_irq_pending[irq_buserror] = 1;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end else cpu_state <= cpu_state_trap;
|
||||
end
|
||||
|
||||
if (!resetn || mem_done) begin
|
||||
|
|
@ -1427,12 +1416,9 @@ module picorv32 #(
|
|||
mem_do_wdata <= 0;
|
||||
end
|
||||
|
||||
if (set_mem_do_rinst)
|
||||
mem_do_rinst <= 1;
|
||||
if (set_mem_do_rdata)
|
||||
mem_do_rdata <= 1;
|
||||
if (set_mem_do_wdata)
|
||||
mem_do_wdata <= 1;
|
||||
if (set_mem_do_rinst) mem_do_rinst <= 1;
|
||||
if (set_mem_do_rdata) mem_do_rdata <= 1;
|
||||
if (set_mem_do_wdata) mem_do_wdata <= 1;
|
||||
|
||||
irq_pending <= next_irq_pending & ~MASKED_IRQ;
|
||||
current_pc = 'bx;
|
||||
|
|
@ -1440,7 +1426,8 @@ module picorv32 #(
|
|||
endmodule
|
||||
|
||||
module picorv32_regs (
|
||||
input clk, wen,
|
||||
input clk,
|
||||
wen,
|
||||
input [5:0] waddr,
|
||||
input [5:0] raddr1,
|
||||
input [5:0] raddr2,
|
||||
|
|
@ -1448,9 +1435,8 @@ module picorv32_regs (
|
|||
output [31:0] rdata1,
|
||||
output [31:0] rdata2
|
||||
);
|
||||
reg [31:0] regs [0:35];
|
||||
always @(posedge clk)
|
||||
if (wen) regs[waddr[5:0]] <= wdata;
|
||||
reg [31:0] regs[0:35];
|
||||
always @(posedge clk) if (wen) regs[waddr[5:0]] <= wdata;
|
||||
assign rdata1 = regs[raddr1];
|
||||
assign rdata2 = regs[raddr2];
|
||||
endmodule
|
||||
|
|
@ -1463,7 +1449,8 @@ module picorv32_pcpi_mul #(
|
|||
parameter STEPS_AT_ONCE = 1,
|
||||
parameter CARRY_CHAIN = 4
|
||||
) (
|
||||
input clk, resetn,
|
||||
input clk,
|
||||
resetn,
|
||||
|
||||
input pcpi_valid,
|
||||
input [31:0] pcpi_insn,
|
||||
|
|
@ -1517,7 +1504,7 @@ module picorv32_pcpi_mul #(
|
|||
next_rs1 = rs1;
|
||||
next_rs2 = rs2;
|
||||
|
||||
for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
|
||||
for (i = 0; i < STEPS_AT_ONCE; i = i + 1) begin
|
||||
this_rs2 = next_rs1[0] ? next_rs2 : 0;
|
||||
if (CARRY_CHAIN == 0) begin
|
||||
next_rdt = next_rd ^ next_rdx ^ this_rs2;
|
||||
|
|
@ -1539,17 +1526,12 @@ module picorv32_pcpi_mul #(
|
|||
mul_finish <= 0;
|
||||
if (!resetn) begin
|
||||
mul_waiting <= 1;
|
||||
end else
|
||||
if (mul_waiting) begin
|
||||
if (instr_rs1_signed)
|
||||
rs1 <= $signed(pcpi_rs1);
|
||||
else
|
||||
rs1 <= $unsigned(pcpi_rs1);
|
||||
end else if (mul_waiting) begin
|
||||
if (instr_rs1_signed) rs1 <= $signed(pcpi_rs1);
|
||||
else rs1 <= $unsigned(pcpi_rs1);
|
||||
|
||||
if (instr_rs2_signed)
|
||||
rs2 <= $signed(pcpi_rs2);
|
||||
else
|
||||
rs2 <= $unsigned(pcpi_rs2);
|
||||
if (instr_rs2_signed) rs2 <= $signed(pcpi_rs2);
|
||||
else rs2 <= $unsigned(pcpi_rs2);
|
||||
|
||||
rd <= 0;
|
||||
rdx <= 0;
|
||||
|
|
@ -1585,7 +1567,8 @@ endmodule
|
|||
***************************************************************/
|
||||
|
||||
module picorv32_pcpi_div (
|
||||
input clk, resetn,
|
||||
input clk,
|
||||
resetn,
|
||||
|
||||
input pcpi_valid,
|
||||
input [31:0] pcpi_insn,
|
||||
|
|
@ -1635,24 +1618,20 @@ module picorv32_pcpi_div (
|
|||
|
||||
if (!resetn) begin
|
||||
running <= 0;
|
||||
end else
|
||||
if (start) begin
|
||||
end else if (start) begin
|
||||
running <= 1;
|
||||
dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
|
||||
divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
|
||||
outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
|
||||
quotient <= 0;
|
||||
quotient_msk <= 1 << 31;
|
||||
end else
|
||||
if (!quotient_msk && running) begin
|
||||
end else if (!quotient_msk && running) begin
|
||||
running <= 0;
|
||||
pcpi_ready <= 1;
|
||||
pcpi_wr <= 1;
|
||||
|
||||
if (instr_div || instr_divu)
|
||||
pcpi_rd <= outsign ? -quotient : quotient;
|
||||
else
|
||||
pcpi_rd <= outsign ? -dividend : dividend;
|
||||
if (instr_div || instr_divu) pcpi_rd <= outsign ? -quotient : quotient;
|
||||
else pcpi_rd <= outsign ? -dividend : dividend;
|
||||
|
||||
end else begin
|
||||
if (divisor <= dividend) begin
|
||||
|
|
|
|||
Loading…
Reference in New Issue