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Fixed catching jumps to misaligned insn

This commit is contained in:
Clifford Wolf 2016-11-29 18:30:11 +01:00
parent 17c7da49f4
commit 54a8e4b311
1 changed files with 9 additions and 7 deletions
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16
picorv32.v
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@ -1564,7 +1564,7 @@ module picorv32 #(
latched_branch <= 1; latched_branch <= 1;
latched_store <= 1; latched_store <= 1;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1; reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1; dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
@ -1849,12 +1849,14 @@ module picorv32 #(
irq_pending <= next_irq_pending & ~MASKED_IRQ; irq_pending <= next_irq_pending & ~MASKED_IRQ;
if (COMPRESSED_ISA) begin if (!CATCH_MISALIGN) begin
reg_pc[0] <= 0; if (COMPRESSED_ISA) begin
reg_next_pc[0] <= 0; reg_pc[0] <= 0;
end else begin reg_next_pc[0] <= 0;
reg_pc[1:0] <= 0; end else begin
reg_next_pc[1:0] <= 0; reg_pc[1:0] <= 0;
reg_next_pc[1:0] <= 0;
end
end end
current_pc = 'bx; current_pc = 'bx;
end end