Add spiflash testbench and add support for QSPI and DDR QSPI to SPI flash sim model
This commit is contained in:
Clifford Wolf
parent
82a51bc8a4
commit
571f5d5df7
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@ -1,5 +1,7 @@
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/testbench.vcd
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/testbench.vvp
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/spiflash_tb.vcd
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/spiflash_tb.vvp
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/firmware.elf
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/firmware_vma.elf
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/firmware.hex
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@ -1,14 +1,20 @@
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test: testbench.vvp firmware.hex
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testbench: testbench.vvp firmware.hex
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vvp -N $<
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testbench.vvp: spiflash.v spimemio.v testbench.v top.v ../picorv32.v
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iverilog -s testbench -o $@ $^
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spiflash_tb: spiflash_tb.vvp firmware.hex
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vvp -N $<
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spiflash_tb.vvp: spiflash.v spiflash_tb.v
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iverilog -s testbench -o $@ $^
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prog: design.bin firmware.bin
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iceprog design.bin
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iceprog -o 1M firmware.bin
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testbench.vvp: spiflash.v spimemio.v testbench.v top.v ../picorv32.v
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iverilog -s testbench -o $@ $^
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firmware.elf: firmware.s
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riscv32-unknown-elf-gcc -c -o firmware.elf firmware.s
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@ -32,9 +38,9 @@ design.bin: design.asc
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icepack design.asc design.bin
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clean:
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rm -f testbench.vvp testbench.vcd
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rm -f testbench.vvp testbench.vcd spiflash_tb.vvp spiflash_tb.vcd
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rm -f firmware.elf firmware_vma.elf firmware.hex firmware.bin
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rm -f design.blif design.log design.asc design.rpt design.bin
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.PHONY: test prog clean
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.PHONY: testbench spiflash_tb prog clean
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@ -15,6 +15,13 @@
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*
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* Supported commands:
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* AB, B9, FF, 03, EB, ED
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*
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* Well written SPI flash data sheets:
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* Cypress S25FL064L http://www.cypress.com/file/316661/download
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*
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*/
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module spiflash (
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@ -30,8 +37,10 @@ module spiflash (
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reg [7:0] buffer;
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integer bitcount = 0;
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integer bytecount = 0;
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integer dummycount = 0;
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reg [7:0] spi_cmd;
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reg [7:0] xip_cmd = 0;
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reg [23:0] spi_addr;
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reg [7:0] spi_in;
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@ -40,12 +49,40 @@ module spiflash (
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reg qspi_active = 0;
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reg powered_up = 0;
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reg in_xfer = 0;
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reg spi_miso;
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localparam [3:0] mode_spi = 1;
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localparam [3:0] mode_qspi_rd = 2;
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localparam [3:0] mode_qspi_wr = 3;
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localparam [3:0] mode_qspi_ddr_rd = 4;
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localparam [3:0] mode_qspi_ddr_wr = 5;
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wire spi_mosi = io0;
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assign io1 = spi_miso;
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reg [3:0] mode = 0;
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reg [3:0] next_mode = 0;
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reg io0_oe = 0;
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reg io1_oe = 0;
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reg io2_oe = 0;
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reg io3_oe = 0;
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reg io0_dout = 0;
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reg io1_dout = 0;
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reg io2_dout = 0;
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reg io3_dout = 0;
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assign io0 = io0_oe ? io0_dout : 1'bz;
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assign io1 = io1_oe ? io1_dout : 1'bz;
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assign io2 = io2_oe ? io2_dout : 1'bz;
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assign io3 = io3_oe ? io3_dout : 1'bz;
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wire io0_delayed;
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wire io1_delayed;
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wire io2_delayed;
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wire io3_delayed;
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assign #1 io0_delayed = io0;
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assign #1 io1_delayed = io1;
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assign #1 io2_delayed = io2;
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assign #1 io3_delayed = io3;
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// 16 MB (128Mb) Flash
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reg [7:0] memory [0:16*1024*1024-1];
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@ -60,11 +97,14 @@ module spiflash (
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if (bytecount == 1) begin
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spi_cmd = buffer;
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if (spi_cmd == 8'hAB)
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if (spi_cmd == 8'h ab)
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powered_up = 1;
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if (spi_cmd == 8'hB9)
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if (spi_cmd == 8'h b9)
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powered_up = 0;
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if (spi_cmd == 8'hFF)
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if (spi_cmd == 8'h ff)
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qspi_active = 0;
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end
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@ -84,6 +124,56 @@ module spiflash (
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end
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end
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if (powered_up && spi_cmd == 'h eb) begin
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if (bytecount == 1)
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mode = mode_qspi_rd;
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if (bytecount == 2)
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spi_addr[23:16] = buffer;
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if (bytecount == 3)
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spi_addr[15:8] = buffer;
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if (bytecount == 4)
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spi_addr[7:0] = buffer;
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if (bytecount == 5) begin
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xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
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mode = mode_qspi_wr;
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dummycount = 1;
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end
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if (bytecount >= 5) begin
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buffer = memory[spi_addr];
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spi_addr = spi_addr + 1;
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end
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end
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if (powered_up && spi_cmd == 'h ed) begin
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if (bytecount == 1)
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next_mode = mode_qspi_ddr_rd;
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if (bytecount == 2)
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spi_addr[23:16] = buffer;
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if (bytecount == 3)
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spi_addr[15:8] = buffer;
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if (bytecount == 4)
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spi_addr[7:0] = buffer;
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if (bytecount == 5) begin
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xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
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mode = mode_qspi_ddr_wr;
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dummycount = 1;
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end
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if (bytecount >= 5) begin
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buffer = memory[spi_addr];
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spi_addr = spi_addr + 1;
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end
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end
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spi_out = buffer;
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spi_io_vld = 1;
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@ -96,37 +186,159 @@ module spiflash (
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end
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endtask
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task ddr_rd_edge;
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begin
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buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
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bitcount = bitcount + 4;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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endtask
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task ddr_wr_edge;
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begin
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io0_oe = 1;
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io1_oe = 1;
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io2_oe = 1;
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io3_oe = 1;
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io0_dout = buffer[4];
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io1_dout = buffer[5];
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io2_dout = buffer[6];
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io3_dout = buffer[7];
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buffer = {buffer, 4'h 0};
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bitcount = bitcount + 4;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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endtask
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always @(csb) begin
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if (csb) begin
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if (verbose && in_xfer) begin
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if (verbose) begin
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$display("");
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$fflush;
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end
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buffer = 0;
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in_xfer = 0;
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bitcount = 0;
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bytecount = 0;
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spi_miso = 0;
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mode = mode_spi;
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end else
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if (xip_cmd) begin
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buffer = xip_cmd;
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bitcount = 0;
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bytecount = 1;
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spi_action;
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end
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end
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always @(csb, clk) begin
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spi_io_vld = 0;
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if (!csb && !clk) begin
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spi_miso = buffer[7];
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if (dummycount > 0) begin
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end else
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case (mode)
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mode_spi: begin
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io0_oe = 0;
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io1_oe = 1;
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io2_oe = 0;
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io3_oe = 0;
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io1_dout = buffer[7];
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end
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mode_qspi_rd: begin
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end
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mode_qspi_wr: begin
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io0_oe = 1;
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io1_oe = 1;
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io2_oe = 1;
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io3_oe = 1;
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io0_dout = buffer[4];
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io1_dout = buffer[5];
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io2_dout = buffer[6];
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io3_dout = buffer[7];
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end
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mode_qspi_ddr_rd: begin
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ddr_rd_edge;
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end
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mode_qspi_ddr_wr: begin
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ddr_wr_edge;
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end
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endcase
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if (next_mode) begin
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case (next_mode)
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mode_qspi_ddr_rd: begin
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end
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mode_qspi_ddr_wr: begin
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io0_oe = 1;
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io1_oe = 1;
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io2_oe = 1;
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io3_oe = 1;
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io0_dout = buffer[4];
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io1_dout = buffer[5];
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io2_dout = buffer[6];
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io3_dout = buffer[7];
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end
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endcase
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mode = next_mode;
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next_mode = 0;
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end
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end
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end
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always @(posedge clk) begin
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if (!csb) begin
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buffer = {buffer, spi_mosi};
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if (dummycount > 0) begin
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dummycount = dummycount - 1;
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end else
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case (mode)
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mode_spi: begin
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buffer = {buffer, io0};
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bitcount = bitcount + 1;
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if (bitcount == 8) begin
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in_xfer = 1;
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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mode_qspi_rd, mode_qspi_wr: begin
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buffer = {buffer, io3, io2, io1, io0};
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bitcount = bitcount + 4;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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mode_qspi_ddr_rd: begin
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ddr_rd_edge;
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end
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mode_qspi_ddr_wr: begin
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ddr_wr_edge;
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end
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endcase
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end
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end
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endmodule
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@ -0,0 +1,363 @@
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/*
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* A simple test bench for the SPI flash simulation model
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module testbench;
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reg flash_csb = 1;
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reg flash_clk = 0;
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wire flash_io0;
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wire flash_io1;
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wire flash_io2;
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wire flash_io3;
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reg flash_io0_oe = 0;
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reg flash_io1_oe = 0;
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reg flash_io2_oe = 0;
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reg flash_io3_oe = 0;
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reg flash_io0_dout = 0;
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reg flash_io1_dout = 0;
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reg flash_io2_dout = 0;
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reg flash_io3_dout = 0;
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assign flash_io0 = flash_io0_oe ? flash_io0_dout : 1'bz;
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assign flash_io1 = flash_io1_oe ? flash_io1_dout : 1'bz;
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assign flash_io2 = flash_io2_oe ? flash_io2_dout : 1'bz;
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assign flash_io3 = flash_io3_oe ? flash_io3_dout : 1'bz;
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spiflash uut (
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.csb(flash_csb),
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.clk(flash_clk),
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.io0(flash_io0),
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.io1(flash_io1),
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.io2(flash_io2),
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.io3(flash_io3)
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);
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localparam [23:0] offset = 24'h100000;
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localparam [31:0] word0 = 32'h 01300293;
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localparam [31:0] word1 = 32'h 00502223;
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reg [7:0] rdata;
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integer errcount = 0;
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task expect;
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input [7:0] data;
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begin
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if (data !== rdata) begin
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$display("ERROR: Got %x (%b) but expected %x (%b).", rdata, rdata, data, data);
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errcount = errcount + 1;
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end
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end
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endtask
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task xfer_begin;
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begin
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#50;
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flash_csb = 0;
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$display("-- BEGIN");
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#50;
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end
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endtask
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task xfer_dummy;
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begin
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flash_io0_oe = 0;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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#50;
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flash_clk = 1;
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#50;
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flash_clk = 0;
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#50;
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end
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endtask
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task xfer_end;
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begin
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#50;
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flash_csb = 1;
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flash_io0_oe = 0;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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$display("-- END");
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$display("");
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#50;
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end
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endtask
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task xfer_spi;
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input [7:0] data;
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integer i;
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begin
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flash_io0_oe = 1;
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flash_io1_oe = 0;
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flash_io2_oe = 0;
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flash_io3_oe = 0;
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for (i = 0; i < 8; i=i+1) begin
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flash_io0_dout = data[7-i];
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#50;
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rdata[7-i] = flash_io1;
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flash_clk <= 1;
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#50;
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flash_clk = 0;
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end
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$display("-- SPI SDR %02x %02x", data, rdata);
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#50;
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end
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endtask
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task xfer_qspi_wr;
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input [7:0] data;
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integer i;
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begin
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flash_io0_oe = 1;
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flash_io1_oe = 1;
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flash_io2_oe = 1;
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flash_io3_oe = 1;
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flash_io0_dout = data[4];
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flash_io1_dout = data[5];
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flash_io2_dout = data[6];
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flash_io3_dout = data[7];
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#50;
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flash_clk = 1;
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#50;
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flash_clk = 0;
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flash_io0_dout = data[0];
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flash_io1_dout = data[1];
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flash_io2_dout = data[2];
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flash_io3_dout = data[3];
|
||||
|
||||
#50;
|
||||
flash_clk = 1;
|
||||
#50;
|
||||
flash_clk = 0;
|
||||
|
||||
$display("-- QSPI SDR %02x --", data);
|
||||
#50;
|
||||
end
|
||||
endtask
|
||||
|
||||
task xfer_qspi_rd;
|
||||
integer i;
|
||||
begin
|
||||
flash_io0_oe = 0;
|
||||
flash_io1_oe = 0;
|
||||
flash_io2_oe = 0;
|
||||
flash_io3_oe = 0;
|
||||
|
||||
#50;
|
||||
rdata[4] = flash_io0;
|
||||
rdata[5] = flash_io1;
|
||||
rdata[6] = flash_io2;
|
||||
rdata[7] = flash_io3;
|
||||
flash_clk <= 1;
|
||||
#50;
|
||||
flash_clk = 0;
|
||||
|
||||
#50;
|
||||
rdata[0] = flash_io0;
|
||||
rdata[1] = flash_io1;
|
||||
rdata[2] = flash_io2;
|
||||
rdata[3] = flash_io3;
|
||||
flash_clk <= 1;
|
||||
#50;
|
||||
flash_clk = 0;
|
||||
|
||||
$display("-- QSPI SDR -- %02x", rdata);
|
||||
#50;
|
||||
end
|
||||
endtask
|
||||
|
||||
task xfer_qspi_ddr_wr;
|
||||
input [7:0] data;
|
||||
integer i;
|
||||
begin
|
||||
flash_io0_oe = 1;
|
||||
flash_io1_oe = 1;
|
||||
flash_io2_oe = 1;
|
||||
flash_io3_oe = 1;
|
||||
|
||||
flash_io0_dout <= data[4];
|
||||
flash_io1_dout <= data[5];
|
||||
flash_io2_dout <= data[6];
|
||||
flash_io3_dout <= data[7];
|
||||
|
||||
#50;
|
||||
flash_clk = 1;
|
||||
|
||||
flash_io0_dout <= data[0];
|
||||
flash_io1_dout <= data[1];
|
||||
flash_io2_dout <= data[2];
|
||||
flash_io3_dout <= data[3];
|
||||
|
||||
#50;
|
||||
flash_clk = 0;
|
||||
|
||||
$display("-- QSPI DDR %02x --", data);
|
||||
#50;
|
||||
end
|
||||
endtask
|
||||
|
||||
task xfer_qspi_ddr_rd;
|
||||
integer i;
|
||||
begin
|
||||
flash_io0_oe = 0;
|
||||
flash_io1_oe = 0;
|
||||
flash_io2_oe = 0;
|
||||
flash_io3_oe = 0;
|
||||
|
||||
#50;
|
||||
rdata[4] = flash_io0;
|
||||
rdata[5] = flash_io1;
|
||||
rdata[6] = flash_io2;
|
||||
rdata[7] = flash_io3;
|
||||
flash_clk <= 1;
|
||||
|
||||
#50;
|
||||
rdata[0] = flash_io0;
|
||||
rdata[1] = flash_io1;
|
||||
rdata[2] = flash_io2;
|
||||
rdata[3] = flash_io3;
|
||||
flash_clk <= 0;
|
||||
|
||||
$display("-- QSPI DDR -- %02x", rdata);
|
||||
#50;
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
$dumpfile("spiflash_tb.vcd");
|
||||
$dumpvars(0, testbench);
|
||||
$display("");
|
||||
|
||||
$display("Reset (FFh)");
|
||||
xfer_begin;
|
||||
xfer_spi(8'h ff);
|
||||
xfer_end;
|
||||
|
||||
$display("Power Up (ABh)");
|
||||
xfer_begin;
|
||||
xfer_spi(8'h ab);
|
||||
xfer_end;
|
||||
|
||||
$display("Read Data (03h)");
|
||||
xfer_begin;
|
||||
xfer_spi(8'h 03);
|
||||
xfer_spi(offset[23:16]);
|
||||
xfer_spi(offset[15:8]);
|
||||
xfer_spi(offset[7:0]);
|
||||
xfer_spi(8'h 00); expect(word0[7:0]);
|
||||
xfer_spi(8'h 00); expect(word0[15:8]);
|
||||
xfer_spi(8'h 00); expect(word0[23:16]);
|
||||
xfer_spi(8'h 00); expect(word0[31:24]);
|
||||
xfer_spi(8'h 00); expect(word1[7:0]);
|
||||
xfer_spi(8'h 00); expect(word1[15:8]);
|
||||
xfer_spi(8'h 00); expect(word1[23:16]);
|
||||
xfer_spi(8'h 00); expect(word1[31:24]);
|
||||
xfer_end;
|
||||
|
||||
$display("Quad I/O Read (EBh)");
|
||||
xfer_begin;
|
||||
xfer_spi(8'h eb);
|
||||
xfer_qspi_wr(offset[23:16]);
|
||||
xfer_qspi_wr(offset[15:8]);
|
||||
xfer_qspi_wr(offset[7:0]);
|
||||
xfer_qspi_wr(8'h a5);
|
||||
xfer_dummy;
|
||||
xfer_qspi_rd; expect(word0[7:0]);
|
||||
xfer_qspi_rd; expect(word0[15:8]);
|
||||
xfer_qspi_rd; expect(word0[23:16]);
|
||||
xfer_qspi_rd; expect(word0[31:24]);
|
||||
xfer_qspi_rd; expect(word1[7:0]);
|
||||
xfer_qspi_rd; expect(word1[15:8]);
|
||||
xfer_qspi_rd; expect(word1[23:16]);
|
||||
xfer_qspi_rd; expect(word1[31:24]);
|
||||
xfer_end;
|
||||
|
||||
$display("Continous Quad I/O Read");
|
||||
xfer_begin;
|
||||
xfer_qspi_wr(offset[23:16]);
|
||||
xfer_qspi_wr(offset[15:8]);
|
||||
xfer_qspi_wr(offset[7:0]);
|
||||
xfer_qspi_wr(8'h ff);
|
||||
xfer_dummy;
|
||||
xfer_qspi_rd; expect(word0[7:0]);
|
||||
xfer_qspi_rd; expect(word0[15:8]);
|
||||
xfer_qspi_rd; expect(word0[23:16]);
|
||||
xfer_qspi_rd; expect(word0[31:24]);
|
||||
xfer_qspi_rd; expect(word1[7:0]);
|
||||
xfer_qspi_rd; expect(word1[15:8]);
|
||||
xfer_qspi_rd; expect(word1[23:16]);
|
||||
xfer_qspi_rd; expect(word1[31:24]);
|
||||
xfer_end;
|
||||
|
||||
$display("DDR Quad I/O Read (EDh)");
|
||||
xfer_begin;
|
||||
xfer_spi(8'h ed);
|
||||
xfer_qspi_ddr_wr(offset[23:16]);
|
||||
xfer_qspi_ddr_wr(offset[15:8]);
|
||||
xfer_qspi_ddr_wr(offset[7:0]);
|
||||
xfer_qspi_ddr_wr(8'h a5);
|
||||
xfer_dummy;
|
||||
xfer_qspi_ddr_rd; expect(word0[7:0]);
|
||||
xfer_qspi_ddr_rd; expect(word0[15:8]);
|
||||
xfer_qspi_ddr_rd; expect(word0[23:16]);
|
||||
xfer_qspi_ddr_rd; expect(word0[31:24]);
|
||||
xfer_qspi_ddr_rd; expect(word1[7:0]);
|
||||
xfer_qspi_ddr_rd; expect(word1[15:8]);
|
||||
xfer_qspi_ddr_rd; expect(word1[23:16]);
|
||||
xfer_qspi_ddr_rd; expect(word1[31:24]);
|
||||
xfer_end;
|
||||
|
||||
$display("Continous DDR Quad I/O Read");
|
||||
xfer_begin;
|
||||
xfer_qspi_ddr_wr(offset[23:16]);
|
||||
xfer_qspi_ddr_wr(offset[15:8]);
|
||||
xfer_qspi_ddr_wr(offset[7:0]);
|
||||
xfer_qspi_ddr_wr(8'h ff);
|
||||
xfer_dummy;
|
||||
xfer_qspi_ddr_rd; expect(word0[7:0]);
|
||||
xfer_qspi_ddr_rd; expect(word0[15:8]);
|
||||
xfer_qspi_ddr_rd; expect(word0[23:16]);
|
||||
xfer_qspi_ddr_rd; expect(word0[31:24]);
|
||||
xfer_qspi_ddr_rd; expect(word1[7:0]);
|
||||
xfer_qspi_ddr_rd; expect(word1[15:8]);
|
||||
xfer_qspi_ddr_rd; expect(word1[23:16]);
|
||||
xfer_qspi_ddr_rd; expect(word1[31:24]);
|
||||
xfer_end;
|
||||
|
||||
#500;
|
||||
|
||||
if (errcount) begin
|
||||
$display("FAIL");
|
||||
$stop;
|
||||
end else begin
|
||||
$display("PASS");
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue