Updated area and timing stats
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README.md
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README.md
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@ -539,13 +539,13 @@ See `make table.txt` in [scripts/vivado/](scripts/vivado/).
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|:-------------------- |:----------:| --------------------:|
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| Xilinx Artix-7T | -1 | 4.8 ns (208 MHz) |
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| Xilinx Artix-7T | -2 | 3.9 ns (256 MHz) |
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| Xilinx Artix-7T | -3 | 3.7 ns (270 MHz) |
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| Xilinx Kintex-7T | -1 | 3.4 ns (294 MHz) |
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| Xilinx Kintex-7T | -2 | 2.7 ns (370 MHz) |
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| Xilinx Artix-7T | -3 | 3.4 ns (294 MHz) |
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| Xilinx Kintex-7T | -1 | 3.2 ns (312 MHz) |
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| Xilinx Kintex-7T | -2 | 2.5 ns (400 MHz) |
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| Xilinx Kintex-7T | -3 | 2.6 ns (384 MHz) |
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| Xilinx Virtex-7T | -1 | 3.0 ns (333 MHz) |
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| Xilinx Virtex-7T | -2 | 2.5 ns (400 MHz) |
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| Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) |
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| Xilinx Virtex-7T | -2 | 2.7 ns (370 MHz) |
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| Xilinx Virtex-7T | -3 | 2.3 ns (434 MHz) |
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#### Utilization on Xilinx 7-Series FPGAs
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@ -553,8 +553,8 @@ The following table lists the resource utilization in area-optimized synthesis
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for the following three cores:
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- **PicoRV32 (small):** The `picorv32` module without counter instructions,
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with externally latched `mem_rdata`, and without catching of misaligned
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memory accesses and illegal instructions.
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without two-stage shifts, with externally latched `mem_rdata`, and without
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catching of misaligned memory accesses and illegal instructions.
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- **PicoRV32 (regular):** The `picorv32` module in its default configuration.
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@ -565,7 +565,7 @@ See `make area` in [scripts/vivado/](scripts/vivado/).
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| Core Variant | Slice LUTs | LUTs as Memory | Slice Registers |
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|:------------------ | ----------:| --------------:| ---------------:|
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| PicoRV32 (small) | 828 | 48 | 422 |
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| PicoRV32 (regular) | 968 | 48 | 564 |
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| PicoRV32 (large) | 1742 | 88 | 1002 |
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| PicoRV32 (small) | 775 | 48 | 422 |
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| PicoRV32 (regular) | 963 | 48 | 564 |
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| PicoRV32 (large) | 1800 | 88 | 1002 |
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@ -14,6 +14,7 @@ module top_small (
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.LATCHED_MEM_RDATA(1),
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.TWO_STAGE_SHIFT(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0)
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) picorv32 (
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