Added asmcheck to scripts/torture/

This commit is contained in:
Clifford Wolf 2016-04-13 16:56:29 +02:00
parent 8d0c9d5b50
commit 6a7ed87d1a
2 changed files with 43 additions and 4 deletions

View File

@ -39,7 +39,7 @@ config.vh: config.py riscv-torture/build.ok
python3 config.py
obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v config.vh
verilator --exe -Wno-fatal --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
verilator --exe -Wno-fatal -DDEBUGASM --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
$(MAKE) -C obj_dir -f Vtestbench.mk
tests/testbench.vvp: testbench.v ../../picorv32.v
@ -64,15 +64,19 @@ tests/test_$(1).elf: tests/test_$(1).S
tests/test_$(1).bin: tests/test_$(1).elf
riscv32-unknown-elf-objcopy -O binary tests/test_$(1).elf tests/test_$(1).bin
tests/test_$(1).dmp: tests/test_$(1).elf
riscv32-unknown-elf-objdump -d tests/test_$(1).elf > tests/test_$(1).dmp
tests/test_$(1).hex: tests/test_$(1).bin
python3 ../../firmware/makehex.py tests/test_$(1).bin 4096 > tests/test_$(1).hex
tests/test_$(1).ref: tests/test_$(1).elf riscv-isa-sim/build.ok
LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike tests/test_$(1).elf > tests/test_$(1).ref
tests/test_$(1).ok: $(TESTBENCH_EXE) tests/test_$(1).hex tests/test_$(1).ref
$(TESTBENCH_EXE) +hex=tests/test_$(1).hex +ref=tests/test_$(1).ref | tee tests/test_$(1).out
grep -q PASSED tests/test_$(1).out
tests/test_$(1).ok: $(TESTBENCH_EXE) tests/test_$(1).hex tests/test_$(1).ref tests/test_$(1).dmp
$(TESTBENCH_EXE) +hex=tests/test_$(1).hex +ref=tests/test_$(1).ref > tests/test_$(1).out
grep -q PASSED tests/test_$(1).out || { cat tests/test_$(1).out; false; }
python3 asmcheck.py tests/test_$(1).out tests/test_$(1).dmp
mv tests/test_$(1).out tests/test_$(1).ok
endef

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@ -0,0 +1,35 @@
#!/usr/bin/env python3
import sys, re
dmp_pattern = re.compile('^\s+([0-9a-f]+):\s+([0-9a-f]+)\s+(\S+)')
disassembled_elf = dict()
def match_insns(s1, s2):
if s1 == "*" or s1 == s2: return True
if s1 == "jal" and s2.startswith("j"): return True
if s1 == "addi" and s2 in ["li", "mv"]: return True
if s1 == "sub" and s2 == "neg": return True
if s1.startswith("b") and s2.startswith("b"): return True
if s1.startswith("s") and s2.startswith("s"): return True
print(s1, s2)
return False
with open(sys.argv[2], "r") as f:
for line in f:
match = dmp_pattern.match(line)
if match:
addr = match.group(1).rjust(8, '0')
opcode = match.group(2).rjust(8, '0')
insn = match.group(3)
disassembled_elf[addr] = (opcode, insn)
with open(sys.argv[1], "r") as f:
for line in f:
line = line.split()
if len(line) < 1 or line[0] != "debugasm":
continue
assert(line[1] in disassembled_elf)
assert(line[2] == disassembled_elf[line[1]][0])
assert(match_insns(line[3], disassembled_elf[line[1]][1]))