From 6af226a385f898395389d71c9faadde130a17853 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Aug 2016 11:24:04 +0200 Subject: [PATCH] Using fast mul in dhrystone benchmark --- README.md | 6 +++--- dhrystone/testbench.v | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 79c12be..bc3fe9b 100644 --- a/README.md +++ b/README.md @@ -345,11 +345,11 @@ When `BARREL_SHIFTER` is activated, a shift operation takes as long as any other ALU operation. The following dhrystone benchmark results are for a core with enabled -`ENABLE_MUL`, `ENABLE_DIV`, and `BARREL_SHIFTER` options. +`ENABLE_FAST_MUL`, `ENABLE_DIV`, and `BARREL_SHIFTER` options. -Dhrystone benchmark results: 0.505 DMIPS/MHz (888 Dhrystones/Second/MHz) +Dhrystone benchmark results: 0.521 DMIPS/MHz (916 Dhrystones/Second/MHz) -For the Dhrystone benchmark the average CPI is 4.208. +For the Dhrystone benchmark the average CPI is 4.081. PicoRV32 Native Memory Interface diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index b767a9e..7744b0d 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -28,7 +28,6 @@ module testbench; picorv32 #( .BARREL_SHIFTER(1), - .ENABLE_MUL(1), .ENABLE_FAST_MUL(1), .ENABLE_DIV(1), .PROGADDR_RESET('h10000),