From 6e318265dc3565b12ed318a72688f7c8ea22d217 Mon Sep 17 00:00:00 2001
From: "colin.liang" <colin.liang@enflame-tech.com>
Date: Thu, 12 Jan 2023 19:00:41 +0800
Subject: [PATCH] format code.

---
 picorv32.v | 27 +++++----------------------
 1 file changed, 5 insertions(+), 22 deletions(-)

diff --git a/picorv32.v b/picorv32.v
index 2abe16f..8de3891 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -357,27 +357,10 @@ module picorv32 #(
   reg instr_lui, instr_auipc, instr_jal, instr_jalr;
   reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
   reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
-  reg
-      instr_addi,
-      instr_slti,
-      instr_sltiu,
-      instr_xori,
-      instr_ori,
-      instr_andi,
-      instr_slli,
-      instr_srli,
-      instr_srai;
-  reg
-      instr_add,
-      instr_sub,
-      instr_sll,
-      instr_slt,
-      instr_sltu,
-      instr_xor,
-      instr_srl,
-      instr_sra,
-      instr_or,
-      instr_and;
+  reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori;
+  reg instr_andi, instr_slli, instr_srli, instr_srai;
+  reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu;
+  reg instr_xor, instr_srl, instr_sra, instr_or, instr_and;
   reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
   reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
   wire instr_trap;
@@ -914,7 +897,7 @@ module picorv32 #(
     set_mem_do_wdata = 0;
 
     alu_out_0_q <= alu_out_0;
-    alu_out_q <= alu_out;
+    alu_out_q   <= alu_out;
 
     if (launch_next_insn) begin
       dbg_rs1val <= 'bx;