diff --git a/scripts/romload/.gitignore b/scripts/romload/.gitignore
new file mode 100644
index 0000000..6f1295b
--- /dev/null
+++ b/scripts/romload/.gitignore
@@ -0,0 +1,11 @@
+firmware.d
+firmware.elf
+firmware.hex
+firmware32.hex
+firmware.o
+firmware_addr.txt
+firmware_dbg.v
+syscalls.o
+testbench.vvp
+testbench.vcd
+start.elf
diff --git a/scripts/romload/Makefile b/scripts/romload/Makefile
new file mode 100644
index 0000000..8db733f
--- /dev/null
+++ b/scripts/romload/Makefile
@@ -0,0 +1,53 @@
+ifndef RISCV_TOOLS_PREFIX
+RISCV_TOOLS_PREFIX = /opt/riscv32ic/bin/riscv32-unknown-elf-
+endif
+CXX = $(RISCV_TOOLS_PREFIX)g++ -march=rv32i
+CC = $(RISCV_TOOLS_PREFIX)gcc -march=rv32i
+AS = $(RISCV_TOOLS_PREFIX)gcc -march=rv32i
+CXXFLAGS = -MD -Os -Wall -std=c++11
+CCFLAGS = -MD -Os -Wall
+#LDFLAGS = -Wl,--gc-sections,--no-relax
+LDFLAGS = -Wl,--gc-sections
+LDLIBS =
+
+test: testbench.vvp firmware32.hex
+	vvp -l testbench.log -N testbench.vvp
+
+testbench.vvp: testbench.v ../../picorv32.v firmware_dbg.v
+	iverilog -D WRITE_VCD=1 -o testbench.vvp testbench.v ../../picorv32.v
+	chmod -x testbench.vvp
+
+firmware32.hex: firmware.elf hex8tohex32.py
+	$(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp
+	python3 hex8tohex32.py firmware.tmp > firmware32.hex
+
+#firmware32.hex: firmware.elf start.elf hex8tohex32.py
+#	$(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp
+#	$(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp
+#	cat start.tmp firmware.tmp > firmware.hex
+#	python3 hex8tohex32.py firmware.hex > firmware32.hex
+#	rm -f start.tmp firmware.tmp
+
+firmware_dbg.v: firmware.map
+	python3 map2debug.py
+#firmware.o: firmware.c
+#	$(CC) -c $^
+
+start.o: start.S
+	$(CC) -c -nostdlib start.S $(LDLIBS)
+
+firmware.elf: firmware.o syscalls.o start.o
+	$(CC) $(LDFLAGS),-Map=firmware.map -o $@ $^ -T sections.lds $(LDLIBS)
+	chmod -x firmware.elf
+
+start.elf: start.S start.ld
+	$(CC) -nostdlib -o start.elf start.S -T start.ld $(LDLIBS)
+	chmod -x start.elf
+
+clean:
+	rm -f *.o *.d *.tmp start.elf
+	rm -f firmware.elf firmware.hex firmware32.hex
+	rm -f testbench.vvp testbench.vcd
+
+-include *.d
+.PHONY: test clean
diff --git a/scripts/romload/sections.lds b/scripts/romload/sections.lds
index ea99ad2..accb2c0 100644
--- a/scripts/romload/sections.lds
+++ b/scripts/romload/sections.lds
@@ -33,7 +33,7 @@ SECTIONS {
           *(.sdata .sdata.*)
            . = ALIGN(4);
           _edata = .;
-        /* } >ram AT>rom */
+        } >ram AT>rom
         /* } >ram */
 
         .bss : {
diff --git a/scripts/romload/start.S b/scripts/romload/start.S
index 73e4ba3..3561384 100644
--- a/scripts/romload/start.S
+++ b/scripts/romload/start.S
@@ -79,7 +79,6 @@ sw zero,12(sp)
 2:
 */
 
-
 /* jump to libc init */
 /*j _ftext
  */
diff --git a/scripts/romload/testbench.v b/scripts/romload/testbench.v
index 1e852cc..8c79e9b 100644
--- a/scripts/romload/testbench.v
+++ b/scripts/romload/testbench.v
@@ -3,7 +3,7 @@
 //`undef WRITE_VCD
 `undef MEM8BIT
 
-`define ROM_SIZE 32'h0000_0000
+`define ROM_SIZE 32'h0001_00FF
 //`define ROM_SIZE 32'h0000_0000
 
 module testbench;
@@ -30,9 +30,7 @@ module testbench;
 
 	picorv32 #(
 		.COMPRESSED_ISA(1),
-		.PROGADDR_RESET(32'h100),
-		.ENABLE_MUL(1),
-		.ENABLE_DIV(1)
+		.PROGADDR_RESET(32'h100)
 	) uut (
 		.clk         (clk        ),
 		.resetn      (resetn     ),
@@ -54,11 +52,19 @@ module testbench;
 	end
 `else
 	reg [31:0] memory [0:MEM_SIZE/4-1];
+`define data_lma   32'hc430
+`define data       32'h20000
+`define edata      32'h209b0
 	integer x;
 	initial
 	begin
+		// clear memory
 		for (x=0; x<MEM_SIZE/4; x=x+1) memory[x] = 0;
+		// load rom contents
 		$readmemh("firmware32.hex", memory);
+		// copy .data section
+		for (x=0; x<(`edata - `data); x=x+4)
+			memory[(`data+x)/4] = memory[(`data_lma+x)/4];
 	end
 `endif