colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Expose ENABLE_IRQ_QREGS and PROGADDR_IRQ from picosoc.v

This commit is contained in:
Olof Kindgren 2018-08-16 22:06:26 +02:00
parent 7c256656c2
commit 75aa1055f8
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
picosoc/picosoc.v
View File

@ -61,9 +61,11 @@ module picosoc (
input flash_io2_di, input flash_io2_di,
input flash_io3_di input flash_io3_di
); );
parameter [0:0] ENABLE_IRQ_QREGS = 0;
parameter integer MEM_WORDS = 256; parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
reg [31:0] irq; reg [31:0] irq;
wire irq_stall = 0; wire irq_stall = 0;
@ -117,13 +119,13 @@ module picosoc (
picorv32 #( picorv32 #(
.STACKADDR(STACKADDR), .STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET), .PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000), .PROGADDR_IRQ(PROGADDR_IRQ),
.BARREL_SHIFTER(1), .BARREL_SHIFTER(1),
.COMPRESSED_ISA(1), .COMPRESSED_ISA(1),
.ENABLE_MUL(1), .ENABLE_MUL(1),
.ENABLE_DIV(1), .ENABLE_DIV(1),
.ENABLE_IRQ(1), .ENABLE_IRQ(1),
.ENABLE_IRQ_QREGS(0) .ENABLE_IRQ_QREGS(ENABLE_IRQ_QREGS)
) cpu ( ) cpu (
.clk (clk ), .clk (clk ),
.resetn (resetn ), .resetn (resetn ),