diff --git a/picorv32.v b/picorv32.v
index d074c4f..ce886d4 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -24,13 +24,6 @@
 
 `timescale 1 ns / 1 ps
 // `default_nettype none
-// `define DEBUG
-
-`ifdef DEBUG
-`define debug(debug_command) debug_command
-`else
-`define debug(debug_command)
-`endif
 
 `define assert(assert_expr) empty_statement
 
@@ -71,11 +64,7 @@ module picorv32 #(
     input             pcpi_wait,
     input             pcpi_ready,
 
-    // IF DEBUG
-    output reg fetch_next,
-    output reg [31:0] dbg_insn_opcode,
-    output reg [31:0] dbg_insn_addr,
-    output reg [63:0] dbg_ascii_instr
+    output reg [7:0] cpu_state
 );
 
   localparam integer regfile_size = 32;
@@ -248,7 +237,6 @@ module picorv32 #(
   reg decoder_trigger;
   reg decoder_trigger_q;
   reg decoder_pseudo_trigger;
-  reg decoder_pseudo_trigger_q;
 
   reg is_lui_auipc_jal;
   reg is_lb_lh_lw_lbu_lhu;
@@ -275,142 +263,7 @@ module picorv32 #(
   wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
   assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
 
-  reg [63:0] new_ascii_instr;
-
-
-  reg [31:0] dbg_insn_imm;
-  reg [4:0] dbg_insn_rs1;
-  reg [4:0] dbg_insn_rs2;
-  reg [4:0] dbg_insn_rd;
-  reg [31:0] dbg_rs1val;
-  reg [31:0] dbg_rs2val;
-  reg dbg_rs1val_valid;
-  reg dbg_rs2val_valid;
-  reg [127:0] dbg_ascii_state;
-
-  always @* begin
-    new_ascii_instr = "";
-
-    if (instr_lui) new_ascii_instr = "lui";
-    if (instr_auipc) new_ascii_instr = "auipc";
-    if (instr_jal) new_ascii_instr = "jal";
-    if (instr_jalr) new_ascii_instr = "jalr";
-
-    if (instr_beq) new_ascii_instr = "beq";
-    if (instr_bne) new_ascii_instr = "bne";
-    if (instr_blt) new_ascii_instr = "blt";
-    if (instr_bge) new_ascii_instr = "bge";
-    if (instr_bltu) new_ascii_instr = "bltu";
-    if (instr_bgeu) new_ascii_instr = "bgeu";
-
-    if (instr_lb) new_ascii_instr = "lb";
-    if (instr_lh) new_ascii_instr = "lh";
-    if (instr_lw) new_ascii_instr = "lw";
-    if (instr_lbu) new_ascii_instr = "lbu";
-    if (instr_lhu) new_ascii_instr = "lhu";
-    if (instr_sb) new_ascii_instr = "sb";
-    if (instr_sh) new_ascii_instr = "sh";
-    if (instr_sw) new_ascii_instr = "sw";
-
-    if (instr_addi) new_ascii_instr = "addi";
-    if (instr_slti) new_ascii_instr = "slti";
-    if (instr_sltiu) new_ascii_instr = "sltiu";
-    if (instr_xori) new_ascii_instr = "xori";
-    if (instr_ori) new_ascii_instr = "ori";
-    if (instr_andi) new_ascii_instr = "andi";
-    if (instr_slli) new_ascii_instr = "slli";
-    if (instr_srli) new_ascii_instr = "srli";
-    if (instr_srai) new_ascii_instr = "srai";
-
-    if (instr_add) new_ascii_instr = "add";
-    if (instr_sub) new_ascii_instr = "sub";
-    if (instr_sll) new_ascii_instr = "sll";
-    if (instr_slt) new_ascii_instr = "slt";
-    if (instr_sltu) new_ascii_instr = "sltu";
-    if (instr_xor) new_ascii_instr = "xor";
-    if (instr_srl) new_ascii_instr = "srl";
-    if (instr_sra) new_ascii_instr = "sra";
-    if (instr_or) new_ascii_instr = "or";
-    if (instr_and) new_ascii_instr = "and";
-
-    if (instr_rdcycle) new_ascii_instr = "rdcycle";
-    if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
-    if (instr_rdinstr) new_ascii_instr = "rdinstr";
-    if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
-
-  end
-
-  reg [63:0] q_ascii_instr;
-  reg [31:0] q_insn_imm;
-  reg [31:0] q_insn_opcode;
-  reg [4:0] q_insn_rs1;
-  reg [4:0] q_insn_rs2;
-  reg [4:0] q_insn_rd;
-
   wire launch_next_insn;
-  reg dbg_valid_insn;
-
-  reg [63:0] cached_ascii_instr;
-  reg [31:0] cached_insn_imm;
-  reg [31:0] cached_insn_opcode;
-  reg [4:0] cached_insn_rs1;
-  reg [4:0] cached_insn_rs2;
-  reg [4:0] cached_insn_rd;
-
-  always @(posedge clk) begin
-    q_ascii_instr <= dbg_ascii_instr;
-    q_insn_imm <= dbg_insn_imm;
-    q_insn_opcode <= dbg_insn_opcode;
-    q_insn_rs1 <= dbg_insn_rs1;
-    q_insn_rs2 <= dbg_insn_rs2;
-    q_insn_rd <= dbg_insn_rd;
-    fetch_next <= launch_next_insn;
-
-    if (!resetn || trap) dbg_valid_insn <= 0;
-    else if (launch_next_insn) dbg_valid_insn <= 1;
-
-    if (decoder_trigger_q) begin
-      cached_ascii_instr <= new_ascii_instr;
-      cached_insn_imm <= decoded_imm;
-      if (&mem_rdata_q[1:0]) cached_insn_opcode <= mem_rdata_q;
-      else cached_insn_opcode <= {16'b0, mem_rdata_q[15:0]};
-      cached_insn_rs1 <= decoded_rs1;
-      cached_insn_rs2 <= decoded_rs2;
-      cached_insn_rd  <= decoded_rd;
-    end
-
-    if (launch_next_insn) begin
-      dbg_insn_addr <= next_pc;
-    end
-  end
-
-  always @* begin
-    dbg_ascii_instr = q_ascii_instr;
-    dbg_insn_imm = q_insn_imm;
-    dbg_insn_opcode = q_insn_opcode;
-    dbg_insn_rs1 = q_insn_rs1;
-    dbg_insn_rs2 = q_insn_rs2;
-    dbg_insn_rd = q_insn_rd;
-
-    if (fetch_next) begin
-      if (decoder_pseudo_trigger_q) begin
-        dbg_ascii_instr = cached_ascii_instr;
-        dbg_insn_imm = cached_insn_imm;
-        dbg_insn_opcode = cached_insn_opcode;
-        dbg_insn_rs1 = cached_insn_rs1;
-        dbg_insn_rs2 = cached_insn_rs2;
-        dbg_insn_rd = cached_insn_rd;
-      end else begin
-        dbg_ascii_instr = new_ascii_instr;
-        if (&mem_rdata_q[1:0]) dbg_insn_opcode = mem_rdata_q;
-        else dbg_insn_opcode = {16'b0, mem_rdata_q[15:0]};
-        dbg_insn_imm = decoded_imm;
-        dbg_insn_rs1 = decoded_rs1;
-        dbg_insn_rs2 = decoded_rs2;
-        dbg_insn_rd  = decoded_rd;
-      end
-    end
-  end
 
   always @(posedge clk) begin
     is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
@@ -574,19 +427,6 @@ module picorv32 #(
   localparam cpu_state_stmem = 8'b00000010;
   localparam cpu_state_ldmem = 8'b00000001;
 
-  reg [7:0] cpu_state;
-
-  always @* begin
-    dbg_ascii_state = "";
-    if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
-    if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
-    if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
-    if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
-    if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
-    if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
-    if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
-    if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
-  end
 
   reg set_mem_do_rinst;
   reg set_mem_do_rdata;
@@ -704,13 +544,6 @@ module picorv32 #(
 
     alu_out_q <= alu_out;
 
-    if (launch_next_insn) begin
-      dbg_rs1val <= 'bx;
-      dbg_rs2val <= 'bx;
-      dbg_rs1val_valid <= 0;
-      dbg_rs2val_valid <= 0;
-    end
-
     if (resetn && pcpi_valid && !pcpi_int_wait) begin
       if (pcpi_timeout_counter) pcpi_timeout_counter <= pcpi_timeout_counter - 1;
     end else pcpi_timeout_counter <= ~0;
@@ -720,7 +553,6 @@ module picorv32 #(
     decoder_trigger <= mem_do_r_inst && mem_done;
     decoder_trigger_q <= decoder_trigger;
     decoder_pseudo_trigger <= 0;
-    decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
 
     if (!resetn) begin
       reg_pc <= PROGADDR_RESET;
@@ -745,23 +577,16 @@ module picorv32 #(
         cpu_state_trap: begin
           trap <= 1;
         end
-
         cpu_state_fetch: begin
           mem_do_r_inst <= !decoder_trigger;
           mem_wordsize  <= 0;
-
           current_pc = reg_next_pc;
-
           (* parallel_case *)
           case (1'b1)
             latched_branch: begin
               current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
-              `debug($display(
-                     "ST_RD:  %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);)
             end
             latched_store && !latched_branch: begin
-              `debug($display("ST_RD:  %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out
-                     );)
             end
           endcase
 
@@ -777,7 +602,6 @@ module picorv32 #(
           latched_rd <= decoded_rd;
 
           if (decoder_trigger) begin
-            `debug($display("-- %-0t", $time);)
             reg_next_pc <= current_pc + 4;
             count_instr <= count_instr + 1;
             if (instr_jal) begin
@@ -799,16 +623,10 @@ module picorv32 #(
           (* parallel_case *)
           case (1'b1)
             instr_trap: begin
-              `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
               reg_op1 <= cpuregs_rs1;
-              dbg_rs1val <= cpuregs_rs1;
-              dbg_rs1val_valid <= 1;
               pcpi_valid <= 1;
-              `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
               reg_sh <= cpuregs_rs2;
               reg_op2 <= cpuregs_rs2;
-              dbg_rs2val <= cpuregs_rs2;
-              dbg_rs2val_valid <= 1;
               if (pcpi_int_ready) begin
                 mem_do_r_inst <= 1;
                 pcpi_valid <= 0;
@@ -817,8 +635,7 @@ module picorv32 #(
                 cpu_state <= cpu_state_fetch;
               end else if (pcpi_timeout || instr_ecall_ebreak) begin
                 pcpi_valid <= 0;
-                `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
-                cpu_state <= cpu_state_trap;
+                cpu_state  <= cpu_state_trap;
               end
             end
             is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
@@ -839,40 +656,25 @@ module picorv32 #(
               cpu_state <= cpu_state_exec;
             end
             is_lb_lh_lw_lbu_lhu && !instr_trap: begin
-              `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
               reg_op1 <= cpuregs_rs1;
-              dbg_rs1val <= cpuregs_rs1;
-              dbg_rs1val_valid <= 1;
               cpu_state <= cpu_state_ldmem;
               mem_do_r_inst <= 1;
             end
             is_slli_srli_srai: begin
-              `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
               reg_op1 <= cpuregs_rs1;
-              dbg_rs1val <= cpuregs_rs1;
-              dbg_rs1val_valid <= 1;
               reg_sh <= decoded_rs2;
               cpu_state <= cpu_state_shift;
             end
             is_jalr_addi_slti_sltiu_xori_ori_andi: begin
-              `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
               reg_op1 <= cpuregs_rs1;
-              dbg_rs1val <= cpuregs_rs1;
-              dbg_rs1val_valid <= 1;
               reg_op2 <= decoded_imm;
               mem_do_r_inst <= mem_do_prefetch;
               cpu_state <= cpu_state_exec;
             end
             default: begin
-              `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
               reg_op1 <= cpuregs_rs1;
-              dbg_rs1val <= cpuregs_rs1;
-              dbg_rs1val_valid <= 1;
-              `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
-              reg_sh <= cpuregs_rs2;
+              reg_sh  <= cpuregs_rs2;
               reg_op2 <= cpuregs_rs2;
-              dbg_rs2val <= cpuregs_rs2;
-              dbg_rs2val_valid <= 1;
               (* parallel_case *)
               case (1'b1)
                 is_sb_sh_sw: begin
@@ -892,12 +694,8 @@ module picorv32 #(
         end
 
         cpu_state_ld_rs2: begin
-          `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
-          reg_sh <= cpuregs_rs2;
+          reg_sh  <= cpuregs_rs2;
           reg_op2 <= cpuregs_rs2;
-          dbg_rs2val <= cpuregs_rs2;
-          dbg_rs2val_valid <= 1;
-
           (* parallel_case *)
           case (1'b1)
             instr_trap: begin
@@ -910,8 +708,7 @@ module picorv32 #(
                 cpu_state <= cpu_state_fetch;
               end else if (pcpi_timeout || instr_ecall_ebreak) begin
                 pcpi_valid <= 0;
-                `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
-                cpu_state <= cpu_state_trap;
+                cpu_state  <= cpu_state_trap;
               end
             end
             is_sb_sh_sw: begin
@@ -946,6 +743,7 @@ module picorv32 #(
             cpu_state <= cpu_state_fetch;
           end
         end
+
         cpu_state_shift: begin
           latched_store <= 1;
           if (reg_sh == 0) begin
@@ -1024,16 +822,13 @@ module picorv32 #(
 
     if (resetn && (mem_do_rdata || mem_do_wdata)) begin
       if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
-        `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
         cpu_state <= cpu_state_trap;
       end
       if (mem_wordsize == 1 && reg_op1[0] != 0) begin
-        `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
         cpu_state <= cpu_state_trap;
       end
     end
     if (resetn && mem_do_r_inst && (|reg_pc[1:0])) begin
-      `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
       cpu_state <= cpu_state_trap;
     end
 
diff --git a/testbench_wb.v b/testbench_wb.v
index 351b458..cd031cb 100644
--- a/testbench_wb.v
+++ b/testbench_wb.v
@@ -73,12 +73,6 @@ module picorv32_wb #(
   wire [31:0] mem_la_wdata;
   wire [ 3:0] mem_la_wstrb;
 
-  // IF DEBUG
-  wire        fetch_next;
-  wire [31:0] dbg_insn_opcode;
-  wire [31:0] dbg_insn_addr;
-  wire [63:0] dbg_ascii_instr;
-
   wire        resetn;
   initial exit = 0;
 
@@ -102,12 +96,8 @@ module picorv32_wb #(
       .mem_la_write(mem_la_write),
       .mem_la_addr (mem_la_addr),
       .mem_la_wdata(mem_la_wdata),
-      .mem_la_wstrb(mem_la_wstrb),
+      .mem_la_wstrb(mem_la_wstrb)
 
-      .fetch_next(fetch_next),
-      .dbg_insn_opcode(dbg_insn_opcode),
-      .dbg_insn_addr(dbg_insn_addr),
-      .dbg_ascii_instr(dbg_ascii_instr)
   );
 
 
@@ -144,25 +134,25 @@ module picorv32_wb #(
     end
   end
 
-  always @(posedge clk) begin
-    if (fetch_next) begin
-      if (&dbg_insn_opcode[1:0])
-        $fwrite(
-            fif,
-            "DECODE: 0x%08x 0x%08x %-0s\n",
-            dbg_insn_addr,
-            dbg_insn_opcode,
-            dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
-        );
-      else
-        $fwrite(
-            fif,
-            "DECODE: 0x%08x     0x%04x %-0s\n",
-            dbg_insn_addr,
-            dbg_insn_opcode[15:0],
-            dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
-        );
-    end
-  end
+  // always @(posedge clk) begin
+  //   if (fetch_next) begin
+  //     if (&dbg_insn_opcode[1:0])
+  //       $fwrite(
+  //           fif,
+  //           "DECODE: 0x%08x 0x%08x %-0s\n",
+  //           dbg_insn_addr,
+  //           dbg_insn_opcode,
+  //           dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
+  //       );
+  //     else
+  //       $fwrite(
+  //           fif,
+  //           "DECODE: 0x%08x     0x%04x %-0s\n",
+  //           dbg_insn_addr,
+  //           dbg_insn_opcode[15:0],
+  //           dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
+  //       );
+  //   end
+  // end
 
 endmodule