Clone vivado dir into quartus dir
This commit is contained in:
Tom Verbeure
parent
9d13c05dd2
commit
7bf87502aa
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@ -0,0 +1,18 @@
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.Xil/
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firmware.bin
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firmware.elf
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firmware.hex
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firmware.map
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synth_*.log
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synth_*.mmi
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synth_*.bit
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synth_system.v
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table.txt
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tab_*/
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webtalk.jou
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webtalk.log
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webtalk_*.jou
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webtalk_*.log
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xelab.*
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xsim.*
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xvlog.*
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VIVADO_BASE = /opt/Xilinx/Vivado/2016.1
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VIVADO = $(VIVADO_BASE)/bin/vivado
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XVLOG = $(VIVADO_BASE)/bin/xvlog
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XELAB = $(VIVADO_BASE)/bin/xelab
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GLBL = $(VIVADO_BASE)/data/verilog/src/glbl.v
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TOOLCHAIN_PREFIX = riscv64-unknown-elf-
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export VIVADO
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help:
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@echo ""
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@echo "Simple synthesis tests:"
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@echo " make synth_area_{small|regular|large}"
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@echo " make synth_speed"
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@echo ""
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@echo "Example system:"
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@echo " make synth_system"
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@echo " make sim_system"
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@echo ""
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@echo "Timing and Utilization Evaluation:"
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@echo " make table.txt"
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@echo " make area"
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@echo ""
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synth_%:
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rm -f $@.log
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$(VIVADO) -nojournal -log $@.log -mode batch -source $@.tcl
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rm -rf .Xil fsm_encoding.os synth_*.backup.log usage_statistics_webtalk.*
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-grep -B4 -A10 'Slice LUTs' $@.log
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-grep -B1 -A9 ^Slack $@.log && echo
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synth_system: firmware.hex
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sim_system:
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$(XVLOG) system_tb.v synth_system.v
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$(XVLOG) $(GLBL)
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$(XELAB) -L unifast_ver -L unisims_ver -R system_tb glbl
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firmware.hex: firmware.S firmware.c firmware.lds
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$(TOOLCHAIN_PREFIX)gcc -Os -m32 -ffreestanding -nostdlib -o firmware.elf firmware.S firmware.c \
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--std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug -lgcc
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$(TOOLCHAIN_PREFIX)objcopy -O binary firmware.elf firmware.bin
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python3 ../../firmware/makehex.py firmware.bin 4096 > firmware.hex
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tab_%/results.txt:
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bash tabtest.sh $@
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area: synth_area_small synth_area_regular synth_area_large
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-grep -B4 -A10 'Slice LUTs' synth_area_small.log synth_area_regular.log synth_area_large.log
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table.txt: tab_small_xc7a_1/results.txt tab_small_xc7a_2/results.txt tab_small_xc7a_3/results.txt
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table.txt: tab_small_xc7k_1/results.txt tab_small_xc7k_2/results.txt tab_small_xc7k_3/results.txt
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table.txt: tab_small_xc7v_1/results.txt tab_small_xc7v_2/results.txt tab_small_xc7v_3/results.txt
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table.txt: tab_small_xcku_1/results.txt tab_small_xcku_2/results.txt tab_small_xcku_3/results.txt
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table.txt: tab_small_xcvu_1/results.txt tab_small_xcvu_2/results.txt tab_small_xcvu_3/results.txt
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table.txt:
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bash table.sh > table.txt
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clean:
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rm -rf .Xil/ firmware.bin firmware.elf firmware.hex firmware.map synth_*.log
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rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/ webtalk.jou
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rm -rf webtalk.log webtalk_*.jou webtalk_*.log xelab.* xsim[._]* xvlog.*
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.section .init
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.global main
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/* set stack pointer */
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lui sp, %hi(16*1024)
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addi sp, sp, %lo(16*1024)
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/* call main */
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jal ra, main
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/* break */
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ebreak
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void putc(char c)
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{
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*(volatile char*)0x10000000 = c;
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}
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void puts(const char *s)
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{
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while (*s) putc(*s++);
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}
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void *memcpy(void *dest, const void *src, int n)
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{
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while (n) {
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n--;
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((char*)dest)[n] = ((char*)src)[n];
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}
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return dest;
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}
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void main()
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{
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char message[] = "$Uryyb+Jbeyq!+Vs+lbh+pna+ernq+guvf+zrffntr+gura$gur+CvpbEI32+PCH"
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"+frrzf+gb+or+jbexvat+whfg+svar.$$++++++++++++++++GRFG+CNFFRQ!$$";
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for (int i = 0; message[i]; i++)
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switch (message[i])
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{
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case 'a' ... 'm':
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case 'A' ... 'M':
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message[i] += 13;
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break;
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case 'n' ... 'z':
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case 'N' ... 'Z':
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message[i] -= 13;
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break;
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case '$':
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message[i] = '\n';
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break;
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case '+':
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message[i] = ' ';
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break;
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}
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puts(message);
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}
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SECTIONS {
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.memory : {
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. = 0x000000;
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*(.init);
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*(.text);
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*(*);
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. = ALIGN(4);
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end = .;
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}
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}
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read_verilog ../../picorv32.v
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read_xdc synth_area.xdc
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synth_design -part xc7k70t-fbg676 -top picorv32_axi
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opt_design -resynth_seq_area
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report_utilization
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report_timing
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create_clock -period 20.00 [get_ports clk]
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read_verilog ../../picorv32.v
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read_verilog synth_area_top.v
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read_xdc synth_area.xdc
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synth_design -part xc7k70t-fbg676 -top top_large
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opt_design -sweep -propconst -resynth_seq_area
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opt_design -directive ExploreSequentialArea
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report_utilization
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report_timing
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read_verilog ../../picorv32.v
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read_verilog synth_area_top.v
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read_xdc synth_area.xdc
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synth_design -part xc7k70t-fbg676 -top top_regular
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opt_design -sweep -propconst -resynth_seq_area
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opt_design -directive ExploreSequentialArea
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report_utilization
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report_timing
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read_verilog ../../picorv32.v
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read_verilog synth_area_top.v
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read_xdc synth_area.xdc
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synth_design -part xc7k70t-fbg676 -top top_small
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opt_design -sweep -propconst -resynth_seq_area
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opt_design -directive ExploreSequentialArea
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report_utilization
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report_timing
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module top_small (
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input clk, resetn,
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output mem_valid,
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output mem_instr,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata
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);
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.LATCHED_MEM_RDATA(1),
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.TWO_STAGE_SHIFT(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0)
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) picorv32 (
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.clk (clk ),
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.resetn (resetn ),
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.mem_valid(mem_valid),
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.mem_instr(mem_instr),
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.mem_ready(mem_ready),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata)
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);
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endmodule
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module top_regular (
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input clk, resetn,
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output trap,
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output mem_valid,
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output mem_instr,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata,
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// Look-Ahead Interface
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output mem_la_read,
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output mem_la_write,
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output [31:0] mem_la_addr,
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output [31:0] mem_la_wdata,
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output [ 3:0] mem_la_wstrb
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);
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picorv32 picorv32 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_la_read (mem_la_read ),
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.mem_la_write(mem_la_write),
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.mem_la_addr (mem_la_addr ),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_wstrb(mem_la_wstrb)
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);
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endmodule
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module top_large (
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input clk, resetn,
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output trap,
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output mem_valid,
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output mem_instr,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata,
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// Look-Ahead Interface
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output mem_la_read,
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output mem_la_write,
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output [31:0] mem_la_addr,
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output [31:0] mem_la_wdata,
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output [ 3:0] mem_la_wstrb,
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// Pico Co-Processor Interface (PCPI)
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output pcpi_valid,
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output [31:0] pcpi_insn,
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output [31:0] pcpi_rs1,
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output [31:0] pcpi_rs2,
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input pcpi_wr,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_ready,
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// IRQ Interface
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input [31:0] irq,
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output [31:0] eoi
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);
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picorv32 #(
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.COMPRESSED_ISA(1),
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.BARREL_SHIFTER(1),
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.ENABLE_PCPI(1),
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.ENABLE_MUL(1),
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.ENABLE_IRQ(1)
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) picorv32 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_la_read (mem_la_read ),
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.mem_la_write (mem_la_write ),
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.mem_la_addr (mem_la_addr ),
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.mem_la_wdata (mem_la_wdata ),
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.mem_la_wstrb (mem_la_wstrb ),
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.pcpi_valid (pcpi_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_wr ),
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.pcpi_rd (pcpi_rd ),
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.pcpi_wait (pcpi_wait ),
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.pcpi_ready (pcpi_ready ),
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.irq (irq ),
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.eoi (eoi )
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);
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endmodule
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read_verilog ../../picorv32.v
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read_xdc synth_speed.xdc
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synth_design -part xc7k70t-fbg676 -top picorv32_axi
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opt_design
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place_design
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phys_opt_design
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route_design
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report_utilization
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report_timing
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@ -0,0 +1 @@
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create_clock -period 2.50 [get_ports clk]
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read_verilog system.v
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read_verilog ../../picorv32.v
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read_xdc synth_system.xdc
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synth_design -part xc7a35t-cpg236-1 -top system
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opt_design
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place_design
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route_design
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report_utilization
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report_timing
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write_verilog -force synth_system.v
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write_bitstream -force synth_system.bit
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# write_mem_info -force synth_system.mmi
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@ -0,0 +1,34 @@
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# XDC File for Basys3 Board
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###########################
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set_property PACKAGE_PIN W5 [get_ports clk]
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set_property IOSTANDARD LVCMOS33 [get_ports clk]
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create_clock -period 10.00 [get_ports clk]
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# Pmod Header JA (JA0..JA7)
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set_property PACKAGE_PIN J1 [get_ports {out_byte[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[0]}]
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set_property PACKAGE_PIN L2 [get_ports {out_byte[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[1]}]
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set_property PACKAGE_PIN J2 [get_ports {out_byte[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[2]}]
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set_property PACKAGE_PIN G2 [get_ports {out_byte[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[3]}]
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set_property PACKAGE_PIN H1 [get_ports {out_byte[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[4]}]
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set_property PACKAGE_PIN K2 [get_ports {out_byte[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[5]}]
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set_property PACKAGE_PIN H2 [get_ports {out_byte[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[6]}]
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set_property PACKAGE_PIN G3 [get_ports {out_byte[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[7]}]
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# Pmod Header JB (JB0..JB2)
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set_property PACKAGE_PIN A14 [get_ports {resetn}]
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set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
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set_property PACKAGE_PIN A16 [get_ports {trap}]
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set_property IOSTANDARD LVCMOS33 [get_ports {trap}]
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set_property PACKAGE_PIN B15 [get_ports {out_byte_en}]
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set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]
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@ -0,0 +1,101 @@
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`timescale 1 ns / 1 ps
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module system (
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input clk,
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input resetn,
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output trap,
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output reg [7:0] out_byte,
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output reg out_byte_en
|
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);
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// set this to 0 for better timing but less performance/MHz
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parameter FAST_MEMORY = 1;
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// 4096 32bit words = 16kB memory
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parameter MEM_SIZE = 4096;
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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wire mem_la_read;
|
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wire mem_la_write;
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wire [31:0] mem_la_addr;
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wire [31:0] mem_la_wdata;
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wire [3:0] mem_la_wstrb;
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picorv32 picorv32_core (
|
||||
.clk (clk ),
|
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.resetn (resetn ),
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.trap (trap ),
|
||||
.mem_valid (mem_valid ),
|
||||
.mem_instr (mem_instr ),
|
||||
.mem_ready (mem_ready ),
|
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.mem_addr (mem_addr ),
|
||||
.mem_wdata (mem_wdata ),
|
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.mem_wstrb (mem_wstrb ),
|
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.mem_rdata (mem_rdata ),
|
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.mem_la_read (mem_la_read ),
|
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.mem_la_write(mem_la_write),
|
||||
.mem_la_addr (mem_la_addr ),
|
||||
.mem_la_wdata(mem_la_wdata),
|
||||
.mem_la_wstrb(mem_la_wstrb)
|
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);
|
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reg [31:0] memory [0:MEM_SIZE-1];
|
||||
initial $readmemh("firmware.hex", memory);
|
||||
|
||||
reg [31:0] m_read_data;
|
||||
reg m_read_en;
|
||||
|
||||
generate if (FAST_MEMORY) begin
|
||||
always @(posedge clk) begin
|
||||
mem_ready <= 1;
|
||||
out_byte_en <= 0;
|
||||
mem_rdata <= memory[mem_la_addr >> 2];
|
||||
if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin
|
||||
if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
|
||||
if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
|
||||
if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
|
||||
if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
|
||||
end
|
||||
else
|
||||
if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
|
||||
out_byte_en <= 1;
|
||||
out_byte <= mem_la_wdata;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk) begin
|
||||
m_read_en <= 0;
|
||||
mem_ready <= mem_valid && !mem_ready && m_read_en;
|
||||
|
||||
m_read_data <= memory[mem_addr >> 2];
|
||||
mem_rdata <= m_read_data;
|
||||
|
||||
out_byte_en <= 0;
|
||||
|
||||
(* parallel_case *)
|
||||
case (1)
|
||||
mem_valid && !mem_ready && !mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
|
||||
m_read_en <= 1;
|
||||
end
|
||||
mem_valid && !mem_ready && |mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
|
||||
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
|
||||
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
|
||||
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
|
||||
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
|
||||
mem_ready <= 1;
|
||||
end
|
||||
mem_valid && !mem_ready && |mem_wstrb && mem_addr == 32'h1000_0000: begin
|
||||
out_byte_en <= 1;
|
||||
out_byte <= mem_wdata;
|
||||
mem_ready <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
`timescale 1 ns / 1 ps
|
||||
|
||||
module system_tb;
|
||||
reg clk = 1;
|
||||
always #5 clk = ~clk;
|
||||
|
||||
reg resetn = 0;
|
||||
initial begin
|
||||
if ($test$plusargs("vcd")) begin
|
||||
$dumpfile("system.vcd");
|
||||
$dumpvars(0, system_tb);
|
||||
end
|
||||
repeat (100) @(posedge clk);
|
||||
resetn <= 1;
|
||||
end
|
||||
|
||||
wire trap;
|
||||
wire [7:0] out_byte;
|
||||
wire out_byte_en;
|
||||
|
||||
system uut (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
.trap (trap ),
|
||||
.out_byte (out_byte ),
|
||||
.out_byte_en(out_byte_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn && out_byte_en) begin
|
||||
$write("%c", out_byte);
|
||||
$fflush;
|
||||
end
|
||||
if (resetn && trap) begin
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
#!/bin/bash
|
||||
|
||||
dashes="----------------------------------------------------------------"
|
||||
printf '| %-25s | %-10s | %-20s |\n' "Device" "Speedgrade" "Clock Period (Freq.)"
|
||||
printf '|:%.25s |:%.10s:| %.20s:|\n' $dashes $dashes $dashes
|
||||
|
||||
for x in $( grep -H . tab_*/results.txt )
|
||||
do
|
||||
read _ size device grade _ speed < <( echo "$x" | tr _/: ' ' )
|
||||
case "$device" in
|
||||
xc7a) d="Xilinx Artix-7T" ;;
|
||||
xc7k) d="Xilinx Kintex-7T" ;;
|
||||
xc7v) d="Xilinx Virtex-7T" ;;
|
||||
xcku) d="Xilinx Kintex UltraScale" ;;
|
||||
xcvu) d="Xilinx Virtex UltraScale" ;;
|
||||
esac
|
||||
speedtxt=$( printf '%s.%s ns (%d MHz)' ${speed%?} ${speed#?} $((10000 / speed)) )
|
||||
printf '| %-25s | %-10s | %20s |\n' "$d" "-$grade" "$speedtxt"
|
||||
done
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
read _ ip dev grade _ < <( echo $* | tr '_/' ' '; )
|
||||
|
||||
# rm -rf tab_${ip}_${dev}_${grade}
|
||||
mkdir -p tab_${ip}_${dev}_${grade}
|
||||
cd tab_${ip}_${dev}_${grade}
|
||||
|
||||
best_speed=99
|
||||
speed=30
|
||||
step=16
|
||||
|
||||
synth_case() {
|
||||
if [ -f test_${1}.txt ]; then
|
||||
echo "Reusing cached tab_${ip}_${dev}_${grade}/test_${1}."
|
||||
return
|
||||
fi
|
||||
|
||||
case "${dev}" in
|
||||
xc7a) xl_device="xc7a15t-fgg484-${grade}" ;;
|
||||
xc7k) xl_device="xc7k70t-fbg676-${grade}" ;;
|
||||
xc7v) xl_device="xc7v585t-ffg1761-${grade}" ;;
|
||||
xcku) xl_device="xcku035-fbva676-${grade}" ;;
|
||||
xcvu) xl_device="xcvu065-ffvc1517-${grade}" ;;
|
||||
esac
|
||||
|
||||
case "${dev}-${grade}" in
|
||||
xcku-1) xl_device="${xl_device}-c" ;;
|
||||
xcvu-1) xl_device="${xl_device}-i" ;;
|
||||
xcku-?|xcvu-?) xl_device="${xl_device}-e" ;;
|
||||
esac
|
||||
|
||||
cat > test_${1}.tcl <<- EOT
|
||||
read_verilog ../tabtest.v
|
||||
read_verilog ../../../picorv32.v
|
||||
read_xdc test_${1}.xdc
|
||||
synth_design -flatten_hierarchy full -part ${xl_device} -top top
|
||||
opt_design -sweep -remap -propconst
|
||||
opt_design -directive Explore
|
||||
place_design -directive Explore
|
||||
phys_opt_design -retime -rewire -critical_pin_opt -placement_opt -critical_cell_opt
|
||||
route_design -directive Explore
|
||||
place_design -post_place_opt
|
||||
phys_opt_design -retime
|
||||
route_design -directive NoTimingRelaxation
|
||||
report_utilization
|
||||
report_timing
|
||||
EOT
|
||||
|
||||
cat > test_${1}.xdc <<- EOT
|
||||
create_clock -period ${speed%?}.${speed#?} [get_ports clk]
|
||||
EOT
|
||||
|
||||
echo "Running tab_${ip}_${dev}_${grade}/test_${1}.."
|
||||
if ! $VIVADO -nojournal -log test_${1}.log -mode batch -source test_${1}.tcl > /dev/null 2>&1; then
|
||||
cat test_${1}.log
|
||||
exit 1
|
||||
fi
|
||||
mv test_${1}.log test_${1}.txt
|
||||
}
|
||||
|
||||
countdown=2
|
||||
while [ $countdown -gt 0 ]; do
|
||||
synth_case $speed
|
||||
|
||||
if grep -q '^Slack.*(VIOLATED)' test_${speed}.txt; then
|
||||
echo " tab_${ip}_${dev}_${grade}/test_${speed} VIOLATED"
|
||||
[ $speed -eq 38 ] || step=$((step / 2))
|
||||
speed=$((speed + step))
|
||||
elif grep -q '^Slack.*(MET)' test_${speed}.txt; then
|
||||
echo " tab_${ip}_${dev}_${grade}/test_${speed} MET"
|
||||
[ $speed -lt $best_speed ] && best_speed=$speed
|
||||
step=$((step / 2))
|
||||
speed=$((speed - step))
|
||||
else
|
||||
echo "ERROR: No slack line found in $PWD/test_${speed}.txt!"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [ $step -eq 0 ]; then
|
||||
countdown=$((countdown - 1))
|
||||
speed=$((best_speed - 2))
|
||||
step=1
|
||||
fi
|
||||
done
|
||||
|
||||
echo "-----------------------"
|
||||
echo "Best speed for tab_${ip}_${dev}_${grade}: $best_speed"
|
||||
echo "-----------------------"
|
||||
echo $best_speed > results.txt
|
||||
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
|
||||
module top (
|
||||
input clk, io_resetn,
|
||||
output io_trap,
|
||||
|
||||
output io_mem_axi_awvalid,
|
||||
input io_mem_axi_awready,
|
||||
output [31:0] io_mem_axi_awaddr,
|
||||
output [ 2:0] io_mem_axi_awprot,
|
||||
|
||||
output io_mem_axi_wvalid,
|
||||
input io_mem_axi_wready,
|
||||
output [31:0] io_mem_axi_wdata,
|
||||
output [ 3:0] io_mem_axi_wstrb,
|
||||
|
||||
input io_mem_axi_bvalid,
|
||||
output io_mem_axi_bready,
|
||||
|
||||
output io_mem_axi_arvalid,
|
||||
input io_mem_axi_arready,
|
||||
output [31:0] io_mem_axi_araddr,
|
||||
output [ 2:0] io_mem_axi_arprot,
|
||||
|
||||
input io_mem_axi_rvalid,
|
||||
output io_mem_axi_rready,
|
||||
input [31:0] io_mem_axi_rdata,
|
||||
|
||||
input [31:0] io_irq,
|
||||
output [31:0] io_eoi
|
||||
);
|
||||
wire resetn;
|
||||
wire trap;
|
||||
wire mem_axi_awvalid;
|
||||
wire mem_axi_awready;
|
||||
wire [31:0] mem_axi_awaddr;
|
||||
wire [2:0] mem_axi_awprot;
|
||||
wire mem_axi_wvalid;
|
||||
wire mem_axi_wready;
|
||||
wire [31:0] mem_axi_wdata;
|
||||
wire [3:0] mem_axi_wstrb;
|
||||
wire mem_axi_bvalid;
|
||||
wire mem_axi_bready;
|
||||
wire mem_axi_arvalid;
|
||||
wire mem_axi_arready;
|
||||
wire [31:0] mem_axi_araddr;
|
||||
wire [2:0] mem_axi_arprot;
|
||||
wire mem_axi_rvalid;
|
||||
wire mem_axi_rready;
|
||||
wire [31:0] mem_axi_rdata;
|
||||
wire [31:0] irq;
|
||||
wire [31:0] eoi;
|
||||
|
||||
delay4 #( 1) delay_resetn (clk, io_resetn , resetn );
|
||||
delay4 #( 1) delay_trap (clk, trap , io_trap );
|
||||
delay4 #( 1) delay_mem_axi_awvalid (clk, mem_axi_awvalid, io_mem_axi_awvalid);
|
||||
delay4 #( 1) delay_mem_axi_awready (clk, io_mem_axi_awready, mem_axi_awready);
|
||||
delay4 #(32) delay_mem_axi_awaddr (clk, mem_axi_awaddr , io_mem_axi_awaddr );
|
||||
delay4 #( 3) delay_mem_axi_awprot (clk, mem_axi_awprot , io_mem_axi_awprot );
|
||||
delay4 #( 1) delay_mem_axi_wvalid (clk, mem_axi_wvalid , io_mem_axi_wvalid );
|
||||
delay4 #( 1) delay_mem_axi_wready (clk, io_mem_axi_wready , mem_axi_wready );
|
||||
delay4 #(32) delay_mem_axi_wdata (clk, mem_axi_wdata , io_mem_axi_wdata );
|
||||
delay4 #( 4) delay_mem_axi_wstrb (clk, mem_axi_wstrb , io_mem_axi_wstrb );
|
||||
delay4 #( 1) delay_mem_axi_bvalid (clk, io_mem_axi_bvalid , mem_axi_bvalid );
|
||||
delay4 #( 1) delay_mem_axi_bready (clk, mem_axi_bready , io_mem_axi_bready );
|
||||
delay4 #( 1) delay_mem_axi_arvalid (clk, mem_axi_arvalid, io_mem_axi_arvalid);
|
||||
delay4 #( 1) delay_mem_axi_arready (clk, io_mem_axi_arready, mem_axi_arready);
|
||||
delay4 #(32) delay_mem_axi_araddr (clk, mem_axi_araddr , io_mem_axi_araddr );
|
||||
delay4 #( 3) delay_mem_axi_arprot (clk, mem_axi_arprot , io_mem_axi_arprot );
|
||||
delay4 #( 1) delay_mem_axi_rvalid (clk, io_mem_axi_rvalid , mem_axi_rvalid );
|
||||
delay4 #( 1) delay_mem_axi_rready (clk, mem_axi_rready , io_mem_axi_rready );
|
||||
delay4 #(32) delay_mem_axi_rdata (clk, io_mem_axi_rdata , mem_axi_rdata );
|
||||
delay4 #(32) delay_irq (clk, io_irq , irq );
|
||||
delay4 #(32) delay_eoi (clk, eoi , io_eoi );
|
||||
|
||||
picorv32_axi #(
|
||||
.TWO_CYCLE_ALU(1)
|
||||
) cpu (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
.trap (trap ),
|
||||
.mem_axi_awvalid(mem_axi_awvalid),
|
||||
.mem_axi_awready(mem_axi_awready),
|
||||
.mem_axi_awaddr (mem_axi_awaddr ),
|
||||
.mem_axi_awprot (mem_axi_awprot ),
|
||||
.mem_axi_wvalid (mem_axi_wvalid ),
|
||||
.mem_axi_wready (mem_axi_wready ),
|
||||
.mem_axi_wdata (mem_axi_wdata ),
|
||||
.mem_axi_wstrb (mem_axi_wstrb ),
|
||||
.mem_axi_bvalid (mem_axi_bvalid ),
|
||||
.mem_axi_bready (mem_axi_bready ),
|
||||
.mem_axi_arvalid(mem_axi_arvalid),
|
||||
.mem_axi_arready(mem_axi_arready),
|
||||
.mem_axi_araddr (mem_axi_araddr ),
|
||||
.mem_axi_arprot (mem_axi_arprot ),
|
||||
.mem_axi_rvalid (mem_axi_rvalid ),
|
||||
.mem_axi_rready (mem_axi_rready ),
|
||||
.mem_axi_rdata (mem_axi_rdata ),
|
||||
.irq (irq ),
|
||||
.eoi (eoi )
|
||||
);
|
||||
endmodule
|
||||
|
||||
module delay4 #(
|
||||
parameter WIDTH = 1
|
||||
) (
|
||||
input clk,
|
||||
input [WIDTH-1:0] in,
|
||||
output reg [WIDTH-1:0] out
|
||||
);
|
||||
reg [WIDTH-1:0] q1, q2, q3;
|
||||
always @(posedge clk) begin
|
||||
q1 <= in;
|
||||
q2 <= q1;
|
||||
q3 <= q2;
|
||||
out <= q3;
|
||||
end
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue