From 8174d8fb7e97d6257c4f67267aea0223dba147b5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 15 Nov 2015 23:24:38 +0100
Subject: [PATCH] Towards compressed ISA support

---
 Makefile    | 11 ++++++-----
 picorv32.v  |  4 +++-
 testbench.v |  4 +++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile
index 690418b..5ded656 100644
--- a/Makefile
+++ b/Makefile
@@ -4,6 +4,7 @@ FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/sieve.
 GCC_WARNS  = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
 GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
 TOOLCHAIN_PREFIX = riscv32-unknown-elf-
+# COMPRESSED_ISA = C
 
 test: testbench.exe firmware/firmware.hex
 	vvp -N testbench.exe
@@ -33,15 +34,15 @@ test_synth: testbench_synth.exe firmware/firmware.hex
 	vvp -N testbench_synth.exe
 
 testbench.exe: testbench.v picorv32.v
-	iverilog -o testbench.exe testbench.v picorv32.v
+	iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v picorv32.v
 	chmod -x testbench.exe
 
 testbench_sp.exe: testbench.v picorv32.v
-	iverilog -o testbench_sp.exe -DSP_TEST testbench.v picorv32.v
+	iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v picorv32.v
 	chmod -x testbench_sp.exe
 
 testbench_axi.exe: testbench.v picorv32.v
-	iverilog -o testbench_axi.exe -DAXI_TEST testbench.v picorv32.v
+	iverilog -o testbench_axi.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DAXI_TEST testbench.v picorv32.v
 	chmod -x testbench_axi.exe
 
 testbench_synth.exe: testbench.v synth.v
@@ -65,10 +66,10 @@ firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
 	chmod -x $@
 
 firmware/start.o: firmware/start.S
-	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32IMXcustom -o $@ $<
+	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32IM$(COMPRESSED_ISA)Xcustom -o $@ $<
 
 firmware/%.o: firmware/%.c
-	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32I -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
+	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32I$(COMPRESSED_ISA) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
 
 tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
 	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32IM -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
diff --git a/picorv32.v b/picorv32.v
index 08d2e16..7a5782d 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -231,7 +231,7 @@ module picorv32 #(
 
 	always @(posedge clk) begin
 		if (mem_valid && mem_ready) begin
-			mem_rdata_q <= mem_rdata;
+			mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
 
 			if (COMPRESSED_ISA && mem_do_rinst) begin
 				case (mem_rdata_latched[1:0])
@@ -1456,6 +1456,7 @@ module picorv32_axi #(
 	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
 	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
 	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
 	parameter [ 0:0] CATCH_MISALIGN = 1,
 	parameter [ 0:0] CATCH_ILLINSN = 1,
 	parameter [ 0:0] ENABLE_PCPI = 0,
@@ -1553,6 +1554,7 @@ module picorv32_axi #(
 		.TWO_STAGE_SHIFT     (TWO_STAGE_SHIFT     ),
 		.TWO_CYCLE_COMPARE   (TWO_CYCLE_COMPARE   ),
 		.TWO_CYCLE_ALU       (TWO_CYCLE_ALU       ),
+		.COMPRESSED_ISA      (COMPRESSED_ISA      ),
 		.CATCH_MISALIGN      (CATCH_MISALIGN      ),
 		.CATCH_ILLINSN       (CATCH_ILLINSN       ),
 		.ENABLE_PCPI         (ENABLE_PCPI         ),
diff --git a/testbench.v b/testbench.v
index 4703f3a..c23f6b3 100644
--- a/testbench.v
+++ b/testbench.v
@@ -7,7 +7,6 @@
 
 `timescale 1 ns / 1 ps
 // `define VERBOSE
-// `define AXI_TEST
 
 module testbench;
 
@@ -54,6 +53,9 @@ module testbench;
 	picorv32_axi #(
 `ifdef SP_TEST
 		.ENABLE_REGS_DUALPORT(0),
+`endif
+`ifdef COMPRESSED_ISA
+		.COMPRESSED_ISA(1),
 `endif
 		.ENABLE_MUL(1),
 		.ENABLE_IRQ(1)