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Change spiflash pin interfaces to support quad SPI

This commit is contained in:
Clifford Wolf 2017-08-04 21:05:05 +02:00
parent cb87f93cf8
commit 82a51bc8a4
5 changed files with 156 additions and 51 deletions
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10
spiflash/pinout.pcf
View File

@ -3,10 +3,12 @@
set_io clk J3 set_io clk J3
set_io spi_cs R12 set_io flash_csb R12
set_io spi_sclk R11 set_io flash_clk R11
set_io spi_miso P11 set_io flash_io0 P12
set_io spi_mosi P12 set_io flash_io1 P11
set_io flash_io2 T9 # center on J3
set_io flash_io3 P8 # center on J3
# All the GPIO pins below are connected to pins that are floating # All the GPIO pins below are connected to pins that are floating
# on the iCE40-HX8K Breakout Board, expect the marked LED pins. # on the iCE40-HX8K Breakout Board, expect the marked LED pins.

49
spiflash/spiflash.v
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@ -1,8 +1,29 @@
/*
* A simple simulation model for an SPI flash
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module spiflash ( module spiflash (
input spi_cs, input csb,
output reg spi_miso, input clk,
input spi_mosi, inout io0, // MOSI
input spi_sclk inout io1, // MISO
inout io2,
inout io3
); );
localparam verbose = 0; localparam verbose = 0;
@ -17,9 +38,15 @@ module spiflash (
reg [7:0] spi_out; reg [7:0] spi_out;
reg spi_io_vld; reg spi_io_vld;
reg qspi_active = 0;
reg powered_up = 0; reg powered_up = 0;
reg in_xfer = 0; reg in_xfer = 0;
reg spi_miso;
wire spi_mosi = io0;
assign io1 = spi_miso;
// 16 MB (128Mb) Flash // 16 MB (128Mb) Flash
reg [7:0] memory [0:16*1024*1024-1]; reg [7:0] memory [0:16*1024*1024-1];
@ -37,6 +64,8 @@ module spiflash (
powered_up = 1; powered_up = 1;
if (spi_cmd == 8'hB9) if (spi_cmd == 8'hB9)
powered_up = 0; powered_up = 0;
if (spi_cmd == 8'hFF)
qspi_active = 0;
end end
if (powered_up && spi_cmd == 'h03) begin if (powered_up && spi_cmd == 'h03) begin
@ -67,8 +96,8 @@ module spiflash (
end end
endtask endtask
always @(spi_cs) begin always @(csb) begin
if (spi_cs) begin if (csb) begin
if (verbose && in_xfer) begin if (verbose && in_xfer) begin
$display(""); $display("");
$fflush; $fflush;
@ -81,15 +110,15 @@ module spiflash (
end end
end end
always @(spi_cs, spi_sclk) begin always @(csb, clk) begin
spi_io_vld = 0; spi_io_vld = 0;
if (!spi_cs && !spi_sclk) begin if (!csb && !clk) begin
spi_miso = buffer[7]; spi_miso = buffer[7];
end end
end end
always @(posedge spi_sclk) begin always @(posedge clk) begin
if (!spi_cs) begin if (!csb) begin
buffer = {buffer, spi_mosi}; buffer = {buffer, spi_mosi};
bitcount = bitcount + 1; bitcount = bitcount + 1;
if (bitcount == 8) begin if (bitcount == 8) begin

53
spiflash/spimemio.v
View File

@ -1,3 +1,22 @@
/*
* Interface module for SPI flash and PicoRV32 native memory interface
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module spimemio ( module spimemio (
input clk, resetn, input clk, resetn,
@ -6,10 +25,12 @@ module spimemio (
input [23:0] addr, input [23:0] addr,
output reg [31:0] rdata, output reg [31:0] rdata,
output reg spi_cs, output reg flash_csb,
output reg spi_sclk, output reg flash_clk,
output reg spi_mosi, output flash_io0,
input spi_miso input flash_io1,
input flash_io2,
input flash_io3
); );
parameter ENABLE_PREFETCH = 1; parameter ENABLE_PREFETCH = 1;
@ -21,11 +42,17 @@ module spimemio (
reg xfer_wait; reg xfer_wait;
reg prefetch; reg prefetch;
reg spi_mosi;
wire spi_miso;
assign flash_io0 = spi_mosi;
assign spi_miso = flash_io1;
always @(posedge clk) begin always @(posedge clk) begin
ready <= 0; ready <= 0;
if (!resetn) begin if (!resetn) begin
spi_cs <= 1; flash_csb <= 1;
spi_sclk <= 1; flash_clk <= 1;
xfer_cnt <= 8; xfer_cnt <= 8;
buffer <= 8'hAB << 24; buffer <= 8'hAB << 24;
addr_q_vld <= 0; addr_q_vld <= 0;
@ -33,14 +60,14 @@ module spimemio (
prefetch <= 0; prefetch <= 0;
end else end else
if (xfer_cnt) begin if (xfer_cnt) begin
if (spi_cs) begin if (flash_csb) begin
spi_cs <= 0; flash_csb <= 0;
end else end else
if (spi_sclk) begin if (flash_clk) begin
spi_sclk <= 0; flash_clk <= 0;
spi_mosi <= buffer[31]; spi_mosi <= buffer[31];
end else begin end else begin
spi_sclk <= 1; flash_clk <= 1;
buffer <= {buffer, spi_miso}; buffer <= {buffer, spi_miso};
xfer_cnt <= xfer_cnt - 1; xfer_cnt <= xfer_cnt - 1;
end end
@ -59,7 +86,7 @@ module spimemio (
xfer_wait <= 1; xfer_wait <= 1;
prefetch <= 0; prefetch <= 0;
end else begin end else begin
spi_cs <= 1; flash_csb <= 1;
buffer <= {8'h 03, addr}; buffer <= {8'h 03, addr};
addr_q <= addr + 4; addr_q <= addr + 4;
addr_q_vld <= 1; addr_q_vld <= 1;
@ -76,7 +103,7 @@ module spimemio (
prefetch <= 0; prefetch <= 0;
xfer_cnt <= 0; xfer_cnt <= 0;
xfer_wait <= 0; xfer_wait <= 0;
spi_sclk <= 1; flash_clk <= 1;
end end
end end
endmodule endmodule

55
spiflash/testbench.v
View File

@ -1,3 +1,22 @@
/*
* Test bench for the "spiflash" SoC
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module testbench; module testbench;
reg clk = 1; reg clk = 1;
always #5 clk = ~clk; always #5 clk = ~clk;
@ -14,10 +33,12 @@ module testbench;
wire [31:0] gpio_i = 0; wire [31:0] gpio_i = 0;
wire [31:0] gpio_o; wire [31:0] gpio_o;
wire spi_cs; wire flash_csb;
wire spi_sclk; wire flash_clk;
wire spi_mosi; wire flash_io0;
wire spi_miso; wire flash_io1;
wire flash_io2;
wire flash_io3;
always @(gpio_o) begin always @(gpio_o) begin
$write("<GPIO:%02x>", gpio_o[7:0]); $write("<GPIO:%02x>", gpio_o[7:0]);
@ -31,19 +52,23 @@ module testbench;
end end
top uut ( top uut (
.clk (clk ), .clk (clk ),
.gpio_i (gpio_i ), .gpio_i (gpio_i ),
.gpio_o (gpio_o ), .gpio_o (gpio_o ),
.spi_cs (spi_cs ), .flash_csb(flash_csb),
.spi_sclk(spi_sclk), .flash_clk(flash_clk),
.spi_mosi(spi_mosi), .flash_io0(flash_io0),
.spi_miso(spi_miso) .flash_io1(flash_io1),
.flash_io2(flash_io2),
.flash_io3(flash_io3)
); );
spiflash spiflash ( spiflash spiflash (
.spi_cs (spi_cs ), .csb(flash_csb),
.spi_sclk(spi_sclk), .clk(flash_clk),
.spi_mosi(spi_mosi), .io0(flash_io0),
.spi_miso(spi_miso) .io1(flash_io1),
.io2(flash_io2),
.io3(flash_io3)
); );
endmodule endmodule

40
spiflash/top.v
View File

@ -1,3 +1,22 @@
/*
* Top-level for "spiflash" SoC demo
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module top ( module top (
input clk, input clk,
output trap, output trap,
@ -5,10 +24,12 @@ module top (
input [31:0] gpio_i, input [31:0] gpio_i,
output reg [31:0] gpio_o, output reg [31:0] gpio_o,
output spi_cs, output flash_csb,
output spi_sclk, output flash_clk,
output spi_mosi, output flash_io0,
input spi_miso input flash_io1,
input flash_io2,
input flash_io3
); );
parameter integer MEM_WORDS = 256; parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
@ -51,16 +72,17 @@ module top (
spimemio spimemio ( spimemio spimemio (
.clk(clk), .clk(clk),
.resetn(resetn), .resetn(resetn),
.valid (mem_valid && mem_addr[31:30] == 2'b10), .valid (mem_valid && mem_addr[31:30] == 2'b10),
.ready (spimem_ready), .ready (spimem_ready),
.addr (mem_addr[23:0]), .addr (mem_addr[23:0]),
.rdata (spimem_rdata), .rdata (spimem_rdata),
.spi_cs (spi_cs ), .flash_csb (flash_csb),
.spi_sclk (spi_sclk), .flash_clk (flash_clk),
.spi_mosi (spi_mosi), .flash_io0 (flash_io0),
.spi_miso (spi_miso) .flash_io1 (flash_io1),
.flash_io2 (flash_io2),
.flash_io3 (flash_io3)
); );
reg [31:0] memory [0:MEM_WORDS-1]; reg [31:0] memory [0:MEM_WORDS-1];