Added scripts/csmith/ spike support

scripts/csmith/.gitignore

@@ -1,9 +1,12 @@
+riscv-fesvr
+riscv-isa-sim
 output_ref.txt
 output_sim.txt
 platform.info
-start.elf
 test.c
+test.ld
 test.elf
 test.exe
 test.hex
 testbench.exe
+testbench.vcd

scripts/csmith/Makefile

@@ -1,4 +1,5 @@
-RISCV_TOOLS_PREFIX = /opt/riscv32imc/bin/riscv32-unknown-elf-
+RISCV_TOOLS_DIR = /opt/riscv32imc
+RISCV_TOOLS_PREFIX = $(RISCV_TOOLS_DIR)/bin/riscv32-unknown-elf-
 CSMITH_INCDIR = $(shell ls -d /usr/local/include/csmith-* | head -n1)
 CC = $(RISCV_TOOLS_PREFIX)gcc
 
@@ -7,15 +8,28 @@ run: test.exe test.hex testbench.exe
 	vvp -N testbench.exe | tee output_sim.txt
 	diff -u output_ref.txt output_sim.txt
 
+spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test.elf
+	LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf
+
+riscv-fesvr/build.ok:
+	rm -rf riscv-fesvr
+	git clone https://github.com/riscv/riscv-fesvr.git riscv-fesvr
+	+cd riscv-fesvr && git checkout 1c02bd6 && ./configure && make && touch build.ok
+
+riscv-isa-sim/build.ok: riscv-fesvr/build.ok
+	rm -rf riscv-isa-sim
+	git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim
+	cd riscv-isa-sim && git checkout 10ae74e
+	cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-exit.diff
+	cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC
+	+cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok
+
 testbench.exe: testbench.v ../../picorv32.v
 	iverilog -o testbench.exe testbench.v ../../picorv32.v
 	chmod -x testbench.exe
 
-test.hex: start.elf test.elf
-	$(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp
-	$(RISCV_TOOLS_PREFIX)objcopy -O verilog test.elf test.tmp
-	cat start.tmp test.tmp > test.hex
-	rm -f start.tmp test.tmp
+test.hex: test.elf
+	$(RISCV_TOOLS_PREFIX)objcopy -O verilog test.elf test.hex
 
 start.elf: start.S start.ld
 	$(CC) -nostdlib -o start.elf start.S -T start.ld
@@ -24,8 +38,10 @@ start.elf: start.S start.ld
 test.exe: test.c
 	gcc -m32 -o test.exe -w -Os -I $(CSMITH_INCDIR) test.c
 
-test.elf: test.c
-	$(CC) -o test.elf -w -Os -I $(CSMITH_INCDIR) test.c syscalls.c
+test.elf: test.c syscalls.c start.S
+	sed -e '/SECTIONS/,+1 s/{/{ . = 0x00000000; .start : { *(.text.start) } application_entry_point = 0x00010000;/;' \
+		$(RISCV_TOOLS_DIR)/riscv32-unknown-elf/lib/riscv.ld > test.ld
+	$(CC) -o test.elf -w -Os -I $(CSMITH_INCDIR) -T test.ld test.c syscalls.c start.S
 	chmod -x test.elf
 
 test.c:
@@ -34,6 +50,11 @@ test.c:
 	csmith -o test.c
 
 clean:
-	rm -f platform.info test.c test.elf start.elf test.hex test.exe
+	rm -f platform.info test.c test.ld test.elf test.hex test.exe
 	rm -f testbench.exe testbench.vcd output_ref.txt output_sim.txt
 
+mrproper: clean
+	rm -rf riscv-fesvr riscv-isa-sim
+
+.PHONY: run spike clean mrproper
+

scripts/csmith/riscv-isa-sim-exit.diff

@@ -0,0 +1,30 @@
+--- a/riscv/processor.cc
++++ b/riscv/processor.cc
+@@ -201,9 +201,10 @@ void processor_t::set_privilege(reg_t prv)
+ 
+ void processor_t::take_trap(trap_t& t, reg_t epc)
+ {
+-  if (debug)
++  // if (debug)
+     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
+             id, t.name(), epc);
++  exit(1);
+ 
+   // by default, trap to M-mode, unless delegated to S-mode
+   reg_t bit = t.cause();
+--- a/riscv/insns/c_ebreak.h
++++ b/riscv/insns/c_ebreak.h
+@@ -1,2 +1,6 @@
+ require_extension('C');
++
++fprintf(stderr, "sbreak\n");
++exit(0);
++
+ throw trap_breakpoint();
+--- a/riscv/insns/sbreak.h
++++ b/riscv/insns/sbreak.h
+@@ -1 +1,4 @@
++fprintf(stderr, "sbreak\n");
++exit(0);
++
+ throw trap_breakpoint();

scripts/csmith/start.S

@@ -1,8 +1,6 @@
-.section .text
-.global _ftext
-.global _pvstart
+.section .text.start
+.global application_entry_point
 
-_pvstart:
 /* zero-initialize all registers */
 addi x1, zero, 0
 addi x2, zero, 0
@@ -49,4 +47,5 @@ sw zero,8(sp)
 sw zero,12(sp)
 
 /* jump to libc init */
-j _ftext
+j application_entry_point
+

scripts/csmith/start.ld

@@ -1,5 +0,0 @@
-SECTIONS {
-. = 0x00000000;
-.text : { *(.text) }
-_ftext = 0x00010000;
-}

scripts/csmith/testbench.v

@@ -40,7 +40,7 @@ module testbench;
 		.mem_rdata   (mem_rdata  )
 	);
 
-	reg [7:0] memory [0:4*1024*1024];
+	reg [7:0] memory [0:4*1024*1024-1];
 	initial $readmemh("test.hex", memory);
 
 	assign mem_ready = 1;