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Vivado 2015.2 area evaluation

This commit is contained in:
Clifford Wolf 2015-07-01 22:18:20 +02:00
parent e72abc0284
commit 84e2202fef
6 changed files with 15 additions and 20 deletions
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12
README.md
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@ -533,7 +533,7 @@ place&route static timing analysis with `report_timing`.
| Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) | | Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) |
The following table lists the resource utilization in area-optimized synthesis, The following table lists the resource utilization in area-optimized synthesis,
as reported by Vivado 2015.1 post optimization with `report_utilization`. as reported by Vivado 2015.2 post optimization with `report_utilization`.
PicoRV32 "small" is the core without counter instructions, with externally PicoRV32 "small" is the core without counter instructions, with externally
latched `mem_rdata`, and without catching of misaligned memory access and latched `mem_rdata`, and without catching of misaligned memory access and
@ -543,9 +543,9 @@ PicoRV32 "regular" is simply the core with its default settings.
And PicoRV32 "large" is with enabled PCPI, IRQ and MUL features. And PicoRV32 "large" is with enabled PCPI, IRQ and MUL features.
| Core Variant | Slice LUTs | LUTs as Memory | | Core Variant | Slice LUTs | LUTs as Memory | Slice Registers |
|:------------------ | ----------:| --------------:| |:------------------ | ----------:| --------------:| ---------------:|
| PicoRV32 "small" | 828 | 48 | | PicoRV32 "small" | 828 | 48 | 422 |
| PicoRV32 "regular" | 968 | 48 | | PicoRV32 "regular" | 968 | 48 | 564 |
| PicoRV32 "large" | 1742 | 88 | | PicoRV32 "large" | 1742 | 88 | 1002 |

5
scripts/vivado/Makefile
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@ -1,5 +1,5 @@
export VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado export VIVADO = /opt/Xilinx/Vivado/2015.2/bin/vivado
help: help:
@echo "Usage: make {synth_speed|synth_area|synth_soc}" @echo "Usage: make {synth_speed|synth_area|synth_soc}"
@ -14,6 +14,9 @@ synth_%:
tab_%/results.txt: tab_%/results.txt:
bash tabtest.sh $@ bash tabtest.sh $@
area: synth_area_small synth_area_regular synth_area_large
-grep -B4 -A10 'Slice LUTs' synth_area_small.log synth_area_regular.log synth_area_large.log
table.txt: tab_small_xc7a_1/results.txt tab_small_xc7a_2/results.txt tab_small_xc7a_3/results.txt table.txt: tab_small_xc7a_1/results.txt tab_small_xc7a_2/results.txt tab_small_xc7a_3/results.txt
table.txt: tab_small_xc7k_1/results.txt tab_small_xc7k_2/results.txt tab_small_xc7k_3/results.txt table.txt: tab_small_xc7k_1/results.txt tab_small_xc7k_2/results.txt tab_small_xc7k_3/results.txt
table.txt: tab_small_xc7v_1/results.txt tab_small_xc7v_2/results.txt tab_small_xc7v_3/results.txt table.txt: tab_small_xc7v_1/results.txt tab_small_xc7v_2/results.txt tab_small_xc7v_3/results.txt

5
scripts/vivado/synth_area.tcl
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@ -1,11 +1,8 @@
read_verilog ../../picorv32.v read_verilog ../../picorv32.v
read_verilog synth_area_top.v
read_xdc synth_area.xdc read_xdc synth_area.xdc
synth_design -part xc7k70t-fbg676 -top top_large synth_design -part xc7k70t-fbg676 -top picorv32_axi
opt_design -resynth_seq_area opt_design -resynth_seq_area
report_utilization report_utilization
# report_timing # report_timing

5
scripts/vivado/synth_area_large.tcl
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@ -1,10 +1,9 @@
read_verilog ../../picorv32.v read_verilog ../../picorv32.v
read_verilog synth_area_top.v
read_xdc synth_area.xdc read_xdc synth_area.xdc
synth_design -part xc7k70t-fbg676 -top picorv32_axi synth_design -part xc7k70t-fbg676 -top top_large
opt_design -resynth_seq_area opt_design -resynth_seq_area
report_utilization report_utilization
# report_timing # report_timing

4
scripts/vivado/synth_area_regular.tcl
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@ -1,11 +1,9 @@
read_verilog ../../picorv32.v read_verilog ../../picorv32.v
read_verilog synth_area_top.v read_verilog synth_area_top.v
read_xdc synth_area.xdc read_xdc synth_area.xdc
synth_design -part xc7k70t-fbg676 -top top_small synth_design -part xc7k70t-fbg676 -top top_regular
opt_design -resynth_seq_area opt_design -resynth_seq_area
report_utilization report_utilization
# report_timing # report_timing

4
scripts/vivado/synth_area_small.tcl
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@ -1,11 +1,9 @@
read_verilog ../../picorv32.v read_verilog ../../picorv32.v
read_verilog synth_area_top.v read_verilog synth_area_top.v
read_xdc synth_area.xdc read_xdc synth_area.xdc
synth_design -part xc7k70t-fbg676 -top top_regular synth_design -part xc7k70t-fbg676 -top top_small
opt_design -resynth_seq_area opt_design -resynth_seq_area
report_utilization report_utilization
# report_timing # report_timing