Added `debug macro
This commit is contained in:
Clifford Wolf
parent
476046c177
commit
853ce91300
69
picorv32.v
69
picorv32.v
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@ -20,6 +20,12 @@
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`timescale 1 ns / 1 ps
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// `define DEBUG
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`ifdef DEBUG
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`define debug(debug_command) debug_command
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`else
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`define debug(debug_command)
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`endif
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/***************************************************************
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* picorv32
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@ -625,6 +631,7 @@ module picorv32 #(
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cpu_state_trap: begin
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trap <= 1;
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end
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cpu_state_fetch: begin
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mem_do_rinst <= !decoder_trigger && !do_waitirq;
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mem_wordsize <= 0;
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@ -633,15 +640,11 @@ module picorv32 #(
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if (latched_branch) begin
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current_pc = latched_store ? (latched_stalu ? reg_alu_out : reg_out) : reg_next_pc;
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`ifdef DEBUG
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$display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);
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`endif
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`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);)
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cpuregs[latched_rd] <= reg_pc + 4;
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end else
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if (latched_store) begin
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`ifdef DEBUG
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$display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? reg_alu_out : reg_out);
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`endif
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`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? reg_alu_out : reg_out);)
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cpuregs[latched_rd] <= latched_stalu ? reg_alu_out : reg_out;
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end else
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if (ENABLE_IRQ && irq_state[0]) begin
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@ -686,16 +689,12 @@ module picorv32 #(
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do_waitirq <= 1;
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end else
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if (decoder_trigger) begin
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`ifdef DEBUG
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$display("-- %-0t", $time);
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`endif
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`debug($display("-- %-0t", $time);)
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reg_next_pc <= current_pc + 4;
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if (ENABLE_COUNTERS)
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count_instr <= count_instr + 1;
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if (instr_jal) begin
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`ifdef DEBUG
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$display("DECODE: 0x%08x jal", current_pc);
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`endif
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`debug($display("DECODE: 0x%08x jal", current_pc);)
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mem_do_rinst <= 1;
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reg_next_pc <= current_pc + decoded_imm_uj;
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latched_branch <= 1;
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@ -706,12 +705,11 @@ module picorv32 #(
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end
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end
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end
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cpu_state_ld_rs1: begin
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reg_op1 <= 'bx;
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reg_op2 <= 'bx;
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`ifdef DEBUG
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$display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");
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`endif
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`debug($display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");)
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if ((CATCH_ILLINSN || WITH_PCPI) && instr_trap) begin
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if (WITH_PCPI) begin
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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@ -727,9 +725,7 @@ module picorv32 #(
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cpu_state <= cpu_state_fetch;
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end else
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if (CATCH_ILLINSN && pcpi_timeout) begin
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`ifdef DEBUG
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$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
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`endif
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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@ -740,9 +736,7 @@ module picorv32 #(
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cpu_state <= cpu_state_ld_rs2;
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end
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end else begin
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`ifdef DEBUG
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$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
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`endif
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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@ -802,9 +796,7 @@ module picorv32 #(
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timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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cpu_state <= cpu_state_fetch;
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end else begin
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`ifdef DEBUG
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$display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);
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`endif
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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if (is_lb_lh_lw_lbu_lhu) begin
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cpu_state <= cpu_state_ldmem;
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@ -817,9 +809,7 @@ module picorv32 #(
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end else if (ENABLE_REGS_DUALPORT) begin
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`ifdef DEBUG
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$display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);
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`endif
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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if (is_sb_sh_sw) begin
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@ -835,10 +825,9 @@ module picorv32 #(
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cpu_state <= cpu_state_ld_rs2;
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end
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end
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cpu_state_ld_rs2: begin
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`ifdef DEBUG
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$display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);
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`endif
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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if (WITH_PCPI && instr_trap) begin
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@ -851,9 +840,7 @@ module picorv32 #(
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cpu_state <= cpu_state_fetch;
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end else
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if (CATCH_ILLINSN && pcpi_timeout) begin
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`ifdef DEBUG
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$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
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`endif
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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@ -871,6 +858,7 @@ module picorv32 #(
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cpu_state <= cpu_state_exec;
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end
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end
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cpu_state_exec: begin
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latched_store <= alu_out_0;
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latched_branch <= alu_out_0;
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@ -890,6 +878,7 @@ module picorv32 #(
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cpu_state <= cpu_state_fetch;
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end
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end
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cpu_state_shift: begin
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latched_store <= 1;
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if (reg_sh == 0) begin
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@ -914,6 +903,7 @@ module picorv32 #(
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reg_sh <= reg_sh - 1;
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end
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end
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cpu_state_stmem: begin
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if (!mem_do_prefetch || mem_done) begin
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if (!mem_do_wdata) begin
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@ -933,6 +923,7 @@ module picorv32 #(
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end
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end
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end
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cpu_state_ldmem: begin
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latched_store <= 1;
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if (!mem_do_prefetch || mem_done) begin
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@ -966,18 +957,14 @@ module picorv32 #(
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if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
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if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
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`ifdef DEBUG
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$display("MISALIGNED WORD: 0x%08x", reg_op1);
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`endif
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`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
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if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
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next_irq_pending[irq_buserror] = 1;
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end else
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cpu_state <= cpu_state_trap;
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end
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if (mem_wordsize == 1 && reg_op1[0] != 0) begin
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`ifdef DEBUG
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$display("MISALIGNED HALFWORD: 0x%08x", reg_op1);
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`endif
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`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
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if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
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next_irq_pending[irq_buserror] = 1;
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end else
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@ -985,9 +972,7 @@ module picorv32 #(
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end
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end
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if (CATCH_MISALIGN && resetn && mem_do_rinst && reg_pc[1:0] != 0) begin
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`ifdef DEBUG
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$display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);
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`endif
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`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
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next_irq_pending[irq_buserror] = 1;
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end else
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