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Updated Vivado SoC example

This commit is contained in:
Clifford Wolf 2015-06-10 16:48:06 +02:00
parent 26127b45de
commit 8590c7d2a8
5 changed files with 47 additions and 18 deletions
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2
scripts/vivado/.gitignore vendored
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@ -1,2 +1,4 @@
synth_*.log
synth_*.mmi
synth_*.bit
synth_*.v

2
scripts/vivado/Makefile
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@ -6,5 +6,5 @@ help:
synth_%:
$(VIVADO) -nojournal -log $@.log -mode batch -source $@.tcl
rm -rf .Xil fsm_encoding.os synth_*.backup.log
rm -rf .Xil fsm_encoding.os synth_*.backup.log usage_statistics_webtalk.*

16
scripts/vivado/soc_top.v
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@ -4,12 +4,8 @@ module soc_top (
input clk,
input resetn,
output trap,
output [7:0] out_byte,
output reg out_byte_en,
output monitor_valid,
output [31:0] monitor_addr,
output [31:0] monitor_data
output reg [7:0] out_byte,
output reg out_byte_en
);
// 4096 32bit words = 16kB memory
parameter MEM_SIZE = 4096;
@ -46,15 +42,10 @@ module soc_top (
.mem_la_wstrb(mem_la_wstrb)
);
assign monitor_valid = mem_valid;
assign monitor_addr = mem_addr;
assign monitor_data = mem_wstrb ? mem_wdata : mem_rdata;
reg [31:0] memory [0:MEM_SIZE-1];
initial $readmemh("firmware.hex", memory);
// initial $readmemh("firmware.hex", memory);
assign mem_ready = 1;
assign out_byte = mem_wdata[7:0];
always @(posedge clk) begin
out_byte_en <= 0;
@ -68,6 +59,7 @@ module soc_top (
else
if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
out_byte_en <= 1;
out_byte <= mem_la_wdata;
end
end
endmodule

4
scripts/vivado/synth_soc.tcl
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@ -3,7 +3,7 @@ read_verilog soc_top.v
read_verilog ../../picorv32.v
read_xdc synth_soc.xdc
synth_design -part xc7a15t-csg324 -top soc_top
synth_design -part xc7a35t-cpg236-1 -top soc_top
opt_design
place_design
route_design
@ -12,4 +12,6 @@ report_utilization
report_timing
write_verilog -force synth_soc.v
write_bitstream -force synth_soc.bit
# write_mem_info -force synth_soc.mmi

35
scripts/vivado/synth_soc.xdc
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@ -1 +1,34 @@
create_clock -period 5.00 [get_ports clk]
# XDC File for Basys3 Board
###########################
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.00 [get_ports clk]
# Pmod Header JA (JA0..JA7)
set_property PACKAGE_PIN J1 [get_ports {out_byte[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[0]}]
set_property PACKAGE_PIN L2 [get_ports {out_byte[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[1]}]
set_property PACKAGE_PIN J2 [get_ports {out_byte[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[2]}]
set_property PACKAGE_PIN G2 [get_ports {out_byte[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[3]}]
set_property PACKAGE_PIN H1 [get_ports {out_byte[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[4]}]
set_property PACKAGE_PIN K2 [get_ports {out_byte[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[5]}]
set_property PACKAGE_PIN H2 [get_ports {out_byte[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[6]}]
set_property PACKAGE_PIN G3 [get_ports {out_byte[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[7]}]
# Pmod Header JB (JB0..JB2)
set_property PACKAGE_PIN A14 [get_ports {resetn}]
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
set_property PACKAGE_PIN A16 [get_ports {trap}]
set_property IOSTANDARD LVCMOS33 [get_ports {trap}]
set_property PACKAGE_PIN B15 [get_ports {out_byte_en}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]