Renamed testbench_slow_mem to testbench_nola (no look ahead)

This commit is contained in:
Clifford Wolf 2016-09-04 12:27:38 +02:00
parent e403c950b0
commit 85d8401c3d
3 changed files with 11 additions and 7 deletions

2
.gitignore vendored
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@ -10,6 +10,8 @@
/dhrystone/dhry.map /dhrystone/dhry.map
/dhrystone/testbench.vvp /dhrystone/testbench.vvp
/dhrystone/testbench.vcd /dhrystone/testbench.vcd
/dhrystone/testbench_nola.vvp
/dhrystone/testbench_nola.vcd
/dhrystone/timing.vvp /dhrystone/timing.vvp
/dhrystone/timing.txt /dhrystone/timing.txt
/dhrystone/*.d /dhrystone/*.d

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@ -13,8 +13,8 @@ endif
test: testbench.vvp dhry.hex test: testbench.vvp dhry.hex
vvp -N testbench.vvp vvp -N testbench.vvp
test_slow_mem: testbench_slow_mem.vvp dhry.hex test_nola: testbench_nola.vvp dhry.hex
vvp -N testbench_slow_mem.vvp vvp -N testbench_nola.vvp
timing: timing.txt timing: timing.txt
grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \ grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \
@ -27,9 +27,9 @@ testbench.vvp: testbench.v ../picorv32.v
iverilog -o testbench.vvp testbench.v ../picorv32.v iverilog -o testbench.vvp testbench.v ../picorv32.v
chmod -x testbench.vvp chmod -x testbench.vvp
testbench_slow_mem.vvp: testbench_slow_mem.v ../picorv32.v testbench_nola.vvp: testbench_nola.v ../picorv32.v
iverilog -o testbench_slow_mem.vvp testbench_slow_mem.v ../picorv32.v iverilog -o testbench_nola.vvp testbench_nola.v ../picorv32.v
chmod -x testbench_slow_mem.vvp chmod -x testbench_nola.vvp
timing.vvp: testbench.v ../picorv32.v timing.vvp: testbench.v ../picorv32.v
iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v
@ -57,7 +57,7 @@ endif
dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
clean: clean:
rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_slow_mem.vvp rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_nola.vvp
.PHONY: test clean .PHONY: test clean

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@ -1,3 +1,5 @@
// A version of the dhrystone test bench that isn't using the look-ahead interface
`timescale 1 ns / 1 ps `timescale 1 ns / 1 ps
module testbench; module testbench;
@ -79,7 +81,7 @@ module testbench;
end end
initial begin initial begin
$dumpfile("testbench_slow_mem.vcd"); $dumpfile("testbench_nola.vcd");
$dumpvars(0, testbench); $dumpvars(0, testbench);
end end