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Fix bug in picosoc spimemio and some cleanups in hx8kdemo

This commit is contained in:
Clifford Wolf 2017-08-08 12:07:17 +02:00
parent 8821696748
commit 89ad9fc85a
3 changed files with 29 additions and 18 deletions
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16
picosoc/hx8kdemo.pcf
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@ -13,12 +13,12 @@ set_io flash_io3 P8 # center on J3
set_io ser_tx B12 set_io ser_tx B12
set_io ser_rx B10 set_io ser_rx B10
set_io leds[0] B5 # LED0 set_io leds[7] B5 # D9
set_io leds[1] B4 # LED1 set_io leds[6] B4 # D8
set_io leds[2] A2 # LED2 set_io leds[5] A2 # D7
set_io leds[3] A1 # LED3 set_io leds[4] A1 # D6
set_io leds[4] C5 # LED4 set_io leds[3] C5 # D5
set_io leds[5] C4 # LED5 set_io leds[2] C4 # D4
set_io leds[6] B3 # LED6 set_io leds[1] B3 # D3
set_io leds[7] C3 # LED7 set_io leds[0] C3 # D2

13
picosoc/hx8kdemo.v
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@ -62,10 +62,15 @@ module hx8kdemo (
reg [31:0] iomem_rdata; reg [31:0] iomem_rdata;
reg [31:0] gpio; reg [31:0] gpio;
reg [4:0] gpio_shr;
assign leds = gpio >> 12; assign leds = gpio >> gpio_shr;
always @(posedge clk) begin always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
gpio_shr <= 0;
end else begin
iomem_ready <= 0; iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 02) begin if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 02) begin
iomem_ready <= 1; iomem_ready <= 1;
@ -75,9 +80,13 @@ module hx8kdemo (
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16]; if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24]; if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end end
if (&leds && gpio_shr < 10) begin
gpio_shr <= gpio_shr + 1;
end
end
end end
picosoc uut ( picosoc soc (
.clk (clk ), .clk (clk ),
.resetn (resetn ), .resetn (resetn ),

2
picosoc/spimemio.v
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@ -105,6 +105,7 @@ module spimemio (
state <= 0; state <= 0;
xfer_resetn <= 0; xfer_resetn <= 0;
rd_valid <= 0; rd_valid <= 0;
buffer_wen <= 0;
din_cont <= 0; din_cont <= 0;
din_qspi <= 0; din_qspi <= 0;
din_ddr <= 0; din_ddr <= 0;
@ -220,6 +221,7 @@ module spimemio (
rd_inc <= 0; rd_inc <= 0;
rd_valid <= 0; rd_valid <= 0;
xfer_resetn <= 0; xfer_resetn <= 0;
buffer_wen <= 0;
state <= 4; state <= 4;
end end
end end