From 8b3d3390f514854be6acaf3d898f781e56ec1c10 Mon Sep 17 00:00:00 2001 From: "colin.liang" Date: Thu, 12 Jan 2023 16:05:34 +0800 Subject: [PATCH] Remove CATCH_MISALIGN CATCH_ILLINSN. --- picorv32.v | 28 ++++++++-------------------- testbench_wb.v | 1 - 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/picorv32.v b/picorv32.v index 45a6732..58c3648 100644 --- a/picorv32.v +++ b/picorv32.v @@ -51,8 +51,6 @@ ***************************************************************/ module picorv32 #( - parameter [ 0:0] ENABLE_COUNTERS = 1, - parameter [ 0:0] ENABLE_COUNTERS64 = 1, parameter [ 0:0] ENABLE_REGS_16_31 = 1, parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, parameter [ 0:0] LATCHED_MEM_RDATA = 0, @@ -60,8 +58,6 @@ module picorv32 #( parameter [ 0:0] BARREL_SHIFTER = 0, parameter [ 0:0] TWO_CYCLE_COMPARE = 0, parameter [ 0:0] TWO_CYCLE_ALU = 0, - parameter [ 0:0] CATCH_MISALIGN = 1, - parameter [ 0:0] CATCH_ILLINSN = 1, parameter [ 0:0] ENABLE_PCPI = 0, parameter [ 0:0] ENABLE_MUL = 0, parameter [ 0:0] ENABLE_FAST_MUL = 0, @@ -455,7 +451,7 @@ module picorv32 #( reg is_alu_reg_reg; reg is_compare; - assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr, + assign instr_trap = !{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu, instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw, instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai, @@ -1041,7 +1037,7 @@ module picorv32 #( dbg_rs2val_valid <= 0; end - if (WITH_PCPI && CATCH_ILLINSN) begin + if (WITH_PCPI) begin if (resetn && pcpi_valid && !pcpi_int_wait) begin if (pcpi_timeout_counter) pcpi_timeout_counter <= pcpi_timeout_counter - 1; @@ -1191,7 +1187,7 @@ module picorv32 #( (* parallel_case *) case (1'b1) - (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin + instr_trap: begin if (WITH_PCPI) begin `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) reg_op1 <= cpuregs_rs1; @@ -1211,7 +1207,7 @@ module picorv32 #( latched_store <= pcpi_int_wr; cpu_state <= cpu_state_fetch; end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + if (pcpi_timeout || instr_ecall_ebreak) begin pcpi_valid <= 0; `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin @@ -1279,7 +1275,7 @@ module picorv32 #( latched_branch <= 1; latched_store <= 1; `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) - reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1; + reg_out <= cpuregs_rs1 & 32'h fffffffe; dbg_rs1val <= cpuregs_rs1; dbg_rs1val_valid <= 1; cpu_state <= cpu_state_fetch; @@ -1383,7 +1379,7 @@ module picorv32 #( latched_store <= pcpi_int_wr; cpu_state <= cpu_state_fetch; end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + if (pcpi_timeout || instr_ecall_ebreak) begin pcpi_valid <= 0; `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin @@ -1528,7 +1524,7 @@ module picorv32 #( next_irq_pending[irq_timer] = 1; end - if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin + if (resetn && (mem_do_rdata || mem_do_wdata)) begin if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin @@ -1544,16 +1540,13 @@ module picorv32 #( cpu_state <= cpu_state_trap; end end - if (CATCH_MISALIGN && resetn && mem_do_rinst && (|reg_pc[1:0])) begin + if (resetn && mem_do_rinst && (|reg_pc[1:0])) begin `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);) if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin next_irq_pending[irq_buserror] = 1; end else cpu_state <= cpu_state_trap; end - if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin - cpu_state <= cpu_state_trap; - end if (!resetn || mem_done) begin mem_do_prefetch <= 0; @@ -1570,11 +1563,6 @@ module picorv32 #( mem_do_wdata <= 1; irq_pending <= next_irq_pending & ~MASKED_IRQ; - - if (!CATCH_MISALIGN) begin - reg_pc[1:0] <= 0; - reg_next_pc[1:0] <= 0; - end current_pc = 'bx; end endmodule diff --git a/testbench_wb.v b/testbench_wb.v index 08b3259..b6e991d 100644 --- a/testbench_wb.v +++ b/testbench_wb.v @@ -191,7 +191,6 @@ module picorv32_wb #( assign resetn = ~wb_rst_i; picorv32 #( - .CATCH_MISALIGN(0), .ENABLE_MUL(1), .ENABLE_DIV(1), .ENABLE_IRQ(1),