diff --git a/Makefile b/Makefile
index ecf3c80..690418b 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@ TEST_OBJS = $(addsuffix .o,$(basename $(wildcard tests/*.S)))
 FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/sieve.o firmware/multest.o firmware/stats.o
 GCC_WARNS  = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
 GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
-TOOLCHAIN_PREFIX = riscv64-unknown-elf-
+TOOLCHAIN_PREFIX = riscv32-unknown-elf-
 
 test: testbench.exe firmware/firmware.hex
 	vvp -N testbench.exe
@@ -65,13 +65,13 @@ firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
 	chmod -x $@
 
 firmware/start.o: firmware/start.S
-	$(TOOLCHAIN_PREFIX)gcc -c -m32 -o $@ $<
+	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32IMXcustom -o $@ $<
 
 firmware/%.o: firmware/%.c
 	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32I -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
 
 tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
-	$(TOOLCHAIN_PREFIX)gcc -c -m32 -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
+	$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32IM -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
 		-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
 
 toc:
diff --git a/README.md b/README.md
index d2ec1cb..87c41c7 100644
--- a/README.md
+++ b/README.md
@@ -5,6 +5,8 @@ PicoRV32 - A Size-Optimized RISC-V CPU
 PicoRV32 is a CPU core that implements the [RISC-V RV32I Instruction Set](http://riscv.org/).
 
 Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools).
+The examples bundled with PicoRV32 (such as the firmware for `make test`) expect a `riscv32-unknown-elf-` toolchain
+(see [build instructions below](#building-a-pure-rv32i-toolchain)) installed in `$PATH`.
 
 PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
 (a license that is similar in terms to the MIT license or the 2-clause BSD license).
diff --git a/dhrystone/Makefile b/dhrystone/Makefile
index e799037..e42fa17 100644
--- a/dhrystone/Makefile
+++ b/dhrystone/Makefile
@@ -1,6 +1,7 @@
 
 OBJS = start.o dhry_1.o dhry_2.o stdlib.o
 CFLAGS = -MD -O3 -m32 -march=RV32I -ffreestanding -nostdlib -DTIME -DRISCV
+TOOLCHAIN_PREFIX = riscv32-unknown-elf-
 
 test: testbench.exe dhry.hex
 	vvp -N testbench.exe
@@ -21,18 +22,20 @@ dhry.hex: dhry.bin ../firmware/makehex.py
 	python3 ../firmware/makehex.py $< 16384 > $@
 
 dhry.bin: dhry.elf
-	riscv64-unknown-elf-objcopy -O binary $< $@
+	$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
 	chmod -x $@
 	
 dhry.elf: $(OBJS) ../firmware/sections.lds
-	riscv64-unknown-elf-gcc $(CFLAGS) -Wl,-Bstatic,-T,../firmware/sections.lds,-Map,dhry.map,--strip-debug -o $@ $(OBJS) -lgcc
+	$(TOOLCHAIN_PREFIX)gcc $(CFLAGS) -Wl,-Bstatic,-T,../firmware/sections.lds,-Map,dhry.map,--strip-debug -o $@ $(OBJS) -lgcc
 	chmod -x $@
 
 %.o: %.c
-	riscv64-unknown-elf-gcc -c $(CFLAGS) $<
+	$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) $<
 
 %.o: %.S
-	riscv64-unknown-elf-gcc -c $(CFLAGS) $<
+	$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) $<
+
+dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
 
 clean:
 	rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd timing.exe timing.txt