Improved "decoder_trigger" handling
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25
picorv32.v
25
picorv32.v
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@ -160,6 +160,7 @@ module picorv32 #(
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reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
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reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
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reg [31:0] decoded_imm;
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reg [31:0] decoded_imm;
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reg decoder_trigger;
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reg decoder_trigger;
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reg decoder_pseudo_trigger;
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wire [31:0] decoded_imm_uj;
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wire [31:0] decoded_imm_uj;
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assign { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } = $signed({mem_rdata[31:12], 1'b0});
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assign { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } = $signed({mem_rdata[31:12], 1'b0});
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@ -250,8 +251,6 @@ module picorv32 #(
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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decoder_trigger <= 0;
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if (mem_do_rinst && mem_done) begin
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if (mem_do_rinst && mem_done) begin
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instr_lui <= mem_rdata[6:0] == 7'b0110111;
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instr_lui <= mem_rdata[6:0] == 7'b0110111;
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instr_auipc <= mem_rdata[6:0] == 7'b0010111;
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instr_auipc <= mem_rdata[6:0] == 7'b0010111;
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@ -308,11 +307,9 @@ module picorv32 #(
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decoded_rd <= mem_rdata[11:7];
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decoded_rd <= mem_rdata[11:7];
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decoded_rs1 <= mem_rdata[19:15];
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decoded_rs1 <= mem_rdata[19:15];
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decoded_rs2 <= mem_rdata[24:20];
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decoded_rs2 <= mem_rdata[24:20];
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decoder_trigger <= 1;
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end
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end
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if (decoder_trigger) begin
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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(* parallel_case *)
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(* parallel_case *)
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case (1'b1)
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case (1'b1)
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|{instr_lui, instr_auipc}:
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|{instr_lui, instr_auipc}:
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@ -351,8 +348,6 @@ module picorv32 #(
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reg set_mem_do_rinst;
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reg set_mem_do_rinst;
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reg set_mem_do_rdata;
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reg set_mem_do_rdata;
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reg set_mem_do_wdata;
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reg set_mem_do_wdata;
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reg mask_decoder_trigger;
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reg force_decoder_trigger;
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reg latched_store;
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reg latched_store;
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reg latched_stalu;
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reg latched_stalu;
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@ -411,14 +406,15 @@ module picorv32 #(
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set_mem_do_rinst = 0;
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set_mem_do_rinst = 0;
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set_mem_do_rdata = 0;
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set_mem_do_rdata = 0;
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set_mem_do_wdata = 0;
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set_mem_do_wdata = 0;
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mask_decoder_trigger <= 0;
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force_decoder_trigger <= 0;
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reg_alu_out <= alu_out;
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reg_alu_out <= alu_out;
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if (ENABLE_COUNTERS)
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if (ENABLE_COUNTERS)
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count_cycle <= resetn ? count_cycle + 1 : 0;
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count_cycle <= resetn ? count_cycle + 1 : 0;
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decoder_trigger <= mem_do_rinst && mem_done;
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decoder_pseudo_trigger <= 0;
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if (!resetn) begin
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if (!resetn) begin
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reg_pc <= 0;
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reg_pc <= 0;
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reg_next_pc <= 0;
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reg_next_pc <= 0;
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@ -440,7 +436,7 @@ module picorv32 #(
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trap <= 1;
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trap <= 1;
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end
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end
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cpu_state_fetch: begin
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cpu_state_fetch: begin
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mem_do_rinst <= (!decoder_trigger || mask_decoder_trigger) && !force_decoder_trigger;
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mem_do_rinst <= !decoder_trigger;
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mem_wordsize <= 0;
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mem_wordsize <= 0;
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current_pc = reg_next_pc;
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current_pc = reg_next_pc;
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@ -470,7 +466,7 @@ module picorv32 #(
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latched_is_lb <= 0;
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latched_is_lb <= 0;
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latched_rd <= decoded_rd;
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latched_rd <= decoded_rd;
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if ((decoder_trigger && !mask_decoder_trigger) || force_decoder_trigger) begin
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if (decoder_trigger) begin
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`ifdef DEBUG
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`ifdef DEBUG
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$display("DECODE: 0x%08x %-s", current_pc, instruction);
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$display("DECODE: 0x%08x %-s", current_pc, instruction);
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`endif
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`endif
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@ -560,7 +556,7 @@ module picorv32 #(
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if (alu_out_0) begin
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if (alu_out_0) begin
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latched_store <= 1;
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latched_store <= 1;
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latched_branch <= 1;
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latched_branch <= 1;
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mask_decoder_trigger <= 1;
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decoder_trigger <= 0;
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set_mem_do_rinst = 1;
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set_mem_do_rinst = 1;
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end
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end
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end else begin
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end else begin
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@ -608,7 +604,7 @@ module picorv32 #(
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end
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end
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if (!mem_do_prefetch && mem_done) begin
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if (!mem_do_prefetch && mem_done) begin
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_fetch;
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force_decoder_trigger <= 1;
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decoder_trigger <= 1;
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end
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end
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end
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end
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end
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end
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@ -635,7 +631,8 @@ module picorv32 #(
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latched_is_lh: reg_out <= $signed(mem_buffer[15:0]);
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latched_is_lh: reg_out <= $signed(mem_buffer[15:0]);
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latched_is_lb: reg_out <= $signed(mem_buffer[7:0]);
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latched_is_lb: reg_out <= $signed(mem_buffer[7:0]);
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endcase
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endcase
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force_decoder_trigger <= 1;
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decoder_trigger <= 1;
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decoder_pseudo_trigger <= 1;
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_fetch;
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end
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end
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end
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end
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