More README stuff
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README.md
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README.md
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@ -57,6 +57,51 @@ non-branching instructions in an external coprocessor. An implementation
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of a core that implements the `MUL[H[SU|U]]` instructions is provided.
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of a core that implements the `MUL[H[SU|U]]` instructions is provided.
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Files in this Repository:
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-------------------------
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#### README.md
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You are reading it right now.
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#### picorv32.v
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This Verilog file contains the following Verilog modules:
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| Module | Description |
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| ----------------------- | ------------------------------------------------------------- |
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| `picorv32` | The PicoRV32 CPU |
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| `picorv32_axi` | The version of the CPU with AXI4-Lite interface |
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| `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite |
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| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions |
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Simply copy this file into your project.
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#### Makefile and testbench.v
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A basic test environment run `make test`, `make test_sp` and/or `make test_axi` to run
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the test firmware in different environments.
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#### firmware/
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A simple test firmware. This runs the basic tests from `tests/`, some C code, tests IRQ
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handling and the multiply PCPI core.
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All the code in `firmware/` is in the public domain. Simply copy whatever you can use.
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#### tests/
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Simple instruction-level tests from [riscv-tests](https://github.com/riscv/riscv-tests).
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#### dhrystone/
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Another simple test firmware that runs the Dhrystome benchmark.
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#### scripts/
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Various scripts and examples for different (synthesis) tools and hardware architectures.
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Parameters:
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Parameters:
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-----------
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-----------
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@ -0,0 +1 @@
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The Dhrystone benchmark and a verilog testbench to run it.
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@ -0,0 +1,2 @@
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A simple test firmware. This code is in the public domain. Simply copy whatever
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you can use.
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@ -1,3 +1,10 @@
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// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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`timescale 1 ns / 1 ps
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`timescale 1 ns / 1 ps
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// `define VERBOSE
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// `define VERBOSE
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// `define AXI_TEST
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// `define AXI_TEST
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