Refactoring of IRQ handling
This commit is contained in:
Clifford Wolf
parent
9d26ebcf58
commit
9a4a06d981
73
README.md
73
README.md
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@ -83,24 +83,19 @@ transaction. In the default configuration the PicoRV32 core only expects the
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`mem_rdata` input to be valid in the cycle with `mem_valid && mem_ready` and
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latches the value internally.
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#### ENABLE_EXTERNAL_IRQ (default = 0)
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#### ENABLE_IRQ (default = 0)
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Set this to 1 to enable external IRQs.
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Set this to 1 to enable IRQs.
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#### ENABLE_ILLINSTR_IRQ (default = 0)
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#### MASKED_IRQ (default = 32'h 0000_0000)
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Set this to 1 to enable the illegal instruction IRQ. This can be used for
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software implementations of instructions such as `MUL` and `DIV`.
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A 1 bit in this bitmask corresponds to a permanently disabled IRQ.
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#### ENABLE_TIMER_IRQ (default = 0)
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Set this to 1 to enable the built-in timer and timer IRQ.
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#### PROGADDR_RESET (default = 0)
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#### PROGADDR_RESET (default = 32'h 0000_0000)
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The start address of the program.
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#### PROGADDR_IRQ (default = 16)
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#### PROGADDR_IRQ (default = 32'h 0000_0010)
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The start address of the interrupt handler.
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@ -141,11 +136,30 @@ Custom Instructions for IRQ Handling
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The following custom instructions are supported when IRQs are enabled.
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The PicoRV32 core has a built-in interrupt controller with 32 interrupts. An
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interrupt can be triggered by asserting the corresponding bit in the `irq`
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input of the core.
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When the interrupt handler is started, the `eoi` End Of Interrupt (EOI) signals
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for the handled interrupts goes high. The `eoi` signal goes low again when the
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interrupt handler returns.
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The IRQs 0-2 can be triggered internally and have the following meaning:
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| IRQ | Interrupt Source |
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| ---:| -----------------------------------|
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| 0 | Timer Interrupt |
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| 1 | SBREAK or Illegal Instruction |
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| 2 | BUS Error (Unalign Memory Access) |
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The core has 4 additional 32-bit registers `q0 .. q3` that are used for IRQ
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handling. When an IRQ triggers, the register `q0` contains the return address
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and `q1` contains the IRQ number. Registers `q2` and `q3` are uninitialized
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and can be used as temporary storage when saving/restoring register values
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in the IRQ handler.
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and `q1` contains a bitmask of all active IRQs. I.e. one call to the interrupt
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handler might need to service one than more IRQ when more than one bit is set
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in `q1`.
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Registers `q2` and `q3` are uninitialized and can be used as temporary storage
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when saving/restoring register values in the IRQ handler.
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#### getq rd, qs
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@ -182,7 +196,7 @@ Example assembler code using the `custom0` mnemonic:
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#### retirq
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Return from interrupt. This instruction copies the value from `q0`
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to the program counter and enables interrupts. The Instruction is
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to the program counter and re-enables interrupts. The Instruction is
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encoded under the `custom0` opcode:
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0000010 00000 00000 000 00000 0001011
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@ -196,36 +210,26 @@ Example assembler code using the `custom0` mnemonic:
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#### maskirq
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The "IRQ Mask" register contains a birtmask of masked (disabled) interrupts.
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This opcodes writes a new value to the irq mask register and reads the old
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value.
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Enable/disable interrupt sources. The Instruction is encoded under the
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`custom0` opcode:
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0000011 XXXXX 00000 000 00000 0001011
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0000011 00000 XXXXX 000 XXXXX 0001011
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f7 f5 rs f3 rd opcode
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The following interrupt sources occupy the following bits
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in the `f5` field:
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| Bit | Interrupt Source |
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| ------| ---------------------|
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| f5[0] | External IRQ |
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| f5[1] | Timer Interrupt |
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| f5[2] | Illegal Instruction |
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| f5[3] | Reserved |
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| f5[4] | Reserved |
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Set bits in the IRQ mask correspond to enabled interrupt sources.
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| maskirq 0 | custom0 0, 0, 0, 3 |
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| maskirq 1 | custom0 0, 0, 1, 3 |
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| maskirq x1, x2 | custom0 1, 2, 0, 3 |
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The processor starts with all interrupts disabled.
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An illegal instruction while the illegal instruction interrupt is disabled will
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cause the processor to halt.
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An illegal instruction or bus error while the illegal instruction or bus error
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interrupt is disabled will cause the processor to halt.
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#### waitirq (unimplemented)
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@ -243,7 +247,7 @@ Example assembler code using the `custom0` mnemonic:
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#### timer
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Reset the timer counter to a new value. The counter counts down cycles and
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Reset the timer counter to a new value. The counter counts down clock cycles and
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triggers the timer interrupt when transitioning from 1 to 0. Setting the
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counter to zero disables the timer.
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@ -261,6 +265,7 @@ Todos:
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------
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- Optional FENCE support
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- Optional Co-Processor Interface
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- Optional write-through cache
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- Optional support for compressed ISA
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- Improved documentation and examples
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@ -33,7 +33,7 @@ static void print_dec(int val)
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{
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char buffer[10];
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char *p = buffer;
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while (val) {
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while (val || p == buffer) {
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*(p++) = val % 10;
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val = val / 10;
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}
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@ -88,24 +88,28 @@ void sieve()
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}
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}
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void irq(uint32_t *regs, uint32_t irqnum)
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uint32_t *irq(uint32_t *regs, uint32_t irqs)
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{
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static int ext_irq_count = 0;
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static int ext_irq_4_count = 0;
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static int ext_irq_5_count = 0;
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static int timer_irq_count = 0;
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if (irqnum == 0) {
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ext_irq_count++;
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// print_str("[EXT-IRQ]");
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return;
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if ((irqs & (1<<4)) != 0) {
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ext_irq_4_count++;
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// print_str("[EXT-IRQ-4]");
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}
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if (irqnum == 1) {
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if ((irqs & (1<<5)) != 0) {
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ext_irq_5_count++;
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// print_str("[EXT-IRQ-5]");
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}
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if ((irqs & 1) != 0) {
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timer_irq_count++;
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// print_str("[TIMER-IRQ]");
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return;
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}
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if (irqnum == 2)
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if ((irqs & 6) != 0)
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{
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int i, k;
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uint32_t pc = regs[0] - 4;
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@ -114,6 +118,7 @@ void irq(uint32_t *regs, uint32_t irqnum)
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print_str("\n");
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print_str("------------------------------------------------------------\n");
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if ((irqs & 2) != 0) {
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if (instr == 0x00100073) {
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print_str("SBREAK instruction at 0x");
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print_hex(pc);
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@ -125,6 +130,15 @@ void irq(uint32_t *regs, uint32_t irqnum)
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print_hex(instr);
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print_str("\n");
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}
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}
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if ((irqs & 4) != 0) {
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print_str("Bus error in Instruction at 0x");
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print_hex(pc);
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print_str(": 0x");
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print_hex(instr);
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print_str("\n");
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}
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for (i = 0; i < 8; i++)
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for (k = 0; k < 4; k++)
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@ -164,8 +178,12 @@ void irq(uint32_t *regs, uint32_t irqnum)
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print_str("------------------------------------------------------------\n");
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print_str("Number of external IRQs counted: ");
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print_dec(ext_irq_count);
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print_str("Number of fast external IRQs counted: ");
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print_dec(ext_irq_4_count);
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print_str("\n");
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print_str("Number of slow external IRQs counted: ");
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print_dec(ext_irq_5_count);
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print_str("\n");
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print_str("Number of timer IRQs counted: ");
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@ -173,7 +191,8 @@ void irq(uint32_t *regs, uint32_t irqnum)
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print_str("\n");
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__asm__("sbreak");
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return;
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}
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return regs;
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}
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@ -10,7 +10,7 @@
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jal zero,n; n ## _ret:
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reset_vec:
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custom0 0,0,7,3 // maskirq 7
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custom0 0,0,0,3 // maskirq zero, zero
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j start
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nop
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nop
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128
picorv32.v
128
picorv32.v
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@ -26,17 +26,16 @@
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***************************************************************/
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module picorv32 #(
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parameter ENABLE_COUNTERS = 1,
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parameter ENABLE_REGS_16_31 = 1,
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parameter ENABLE_REGS_DUALPORT = 1,
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parameter LATCHED_MEM_RDATA = 0,
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parameter ENABLE_EXTERNAL_IRQ = 0,
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parameter ENABLE_ILLINSTR_IRQ = 0,
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parameter ENABLE_TIMER_IRQ = 0,
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parameter PROGADDR_RESET = 0,
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parameter PROGADDR_IRQ = 16
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010
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) (
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input clk, resetn, irq,
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input clk, resetn,
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output reg trap,
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output reg mem_valid,
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@ -53,9 +52,15 @@ module picorv32 #(
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output mem_la_write,
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output [31:0] mem_la_addr,
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output reg [31:0] mem_la_wdata,
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output reg [ 3:0] mem_la_wstrb
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output reg [ 3:0] mem_la_wstrb,
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// IRQ interface
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input [31:0] irq,
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output reg [31:0] eoi
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);
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localparam ENABLE_IRQ = ENABLE_EXTERNAL_IRQ || ENABLE_ILLINSTR_IRQ || ENABLE_TIMER_IRQ;
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localparam integer irq_timer = 0;
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localparam integer irq_sbreak = 1;
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localparam integer irq_buserror = 2;
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localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
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localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ;
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@ -69,8 +74,8 @@ module picorv32 #(
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wire [31:0] next_pc;
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reg irq_active;
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reg [4:0] irq_mask;
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reg [4:0] irq_pending;
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reg [31:0] irq_mask;
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reg [31:0] irq_pending;
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reg [31:0] timer;
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// Memory Interface
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@ -185,6 +190,7 @@ module picorv32 #(
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reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
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reg [31:0] decoded_imm, decoded_imm_uj;
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reg decoder_trigger;
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reg decoder_trigger_q;
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reg decoder_pseudo_trigger;
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reg is_lui_auipc_jal;
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@ -272,7 +278,7 @@ module picorv32 #(
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if (instr_waitirq) new_instruction = "waitirq";
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if (instr_timer) new_instruction = "timer";
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if (new_instruction)
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if (decoder_trigger_q)
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instruction = new_instruction;
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end
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@ -362,7 +368,7 @@ module picorv32 #(
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instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ;
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instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
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instr_waitirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000100 && ENABLE_IRQ;
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instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_TIMER_IRQ;
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instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ;
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is_slli_srli_srai <= is_alu_reg_imm && |{
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mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
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@ -432,6 +438,8 @@ module picorv32 #(
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reg [31:0] current_pc;
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assign next_pc = latched_store && latched_branch ? reg_out : reg_next_pc;
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reg [31:0] next_irq_pending;
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reg [31:0] alu_out;
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reg alu_out_0;
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@ -484,16 +492,19 @@ module picorv32 #(
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if (ENABLE_COUNTERS)
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count_cycle <= resetn ? count_cycle + 1 : 0;
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if (ENABLE_TIMER_IRQ && timer) begin
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next_irq_pending = irq_pending;
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if (ENABLE_IRQ && timer) begin
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if (timer - 1 == 0)
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irq_pending[1] <= 1;
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next_irq_pending[irq_timer] = 1;
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timer <= timer - 1;
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end
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if (ENABLE_EXTERNAL_IRQ && irq) begin
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irq_pending[0] <= 1;
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if (ENABLE_IRQ) begin
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next_irq_pending = next_irq_pending | irq;
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end
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decoder_trigger_q <= decoder_trigger;
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decoder_trigger <= mem_do_rinst && mem_done;
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decoder_pseudo_trigger <= 0;
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@ -509,9 +520,10 @@ module picorv32 #(
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latched_is_lh <= 0;
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latched_is_lb <= 0;
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irq_active <= 0;
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irq_mask <= 0;
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irq_pending <= 0;
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irq_mask <= ~0;
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next_irq_pending = 0;
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irq_state <= 0;
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eoi <= 0;
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timer <= 0;
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cpu_state <= cpu_state_fetch;
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end else
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@ -546,16 +558,9 @@ module picorv32 #(
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mem_do_rinst <= 1;
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end else
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if (ENABLE_IRQ && irq_state[1]) begin
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cpuregs[latched_rd] <=
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irq_pending[0] && irq_mask[0] ? 0 :
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irq_pending[1] && irq_mask[1] ? 1 :
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irq_pending[2] && irq_mask[2] ? 2 :
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irq_pending[3] && irq_mask[3] ? 3 : 4;
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irq_pending <=
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irq_pending[0] && irq_mask[0] ? irq_pending & 5'b11110 :
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irq_pending[1] && irq_mask[1] ? irq_pending & 5'b11101 :
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irq_pending[2] && irq_mask[2] ? irq_pending & 5'b11011 :
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irq_pending[3] && irq_mask[3] ? irq_pending & 5'b10111 : irq_pending & 5'b01111;
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eoi <= irq_pending & ~irq_mask;
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cpuregs[latched_rd] <= irq_pending & ~irq_mask;
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next_irq_pending = next_irq_pending & irq_mask;
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end
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reg_pc <= current_pc;
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@ -569,7 +574,7 @@ module picorv32 #(
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latched_is_lb <= 0;
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latched_rd <= decoded_rd;
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if (ENABLE_IRQ && ((decoder_trigger && !irq_active && |(irq_pending & irq_mask)) || irq_state)) begin
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if (ENABLE_IRQ && ((decoder_trigger && !irq_active && |(irq_pending & ~irq_mask)) || irq_state)) begin
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irq_state <=
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irq_state == 2'b00 ? 2'b01 :
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irq_state == 2'b01 ? 2'b10 : 2'b00;
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@ -600,14 +605,14 @@ module picorv32 #(
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reg_op1 <= 'bx;
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reg_op2 <= 'bx;
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`ifdef DEBUG
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$display("DECODE: 0x%08x %-0s", reg_pc, instruction);
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$display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");
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`endif
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if (instr_trap) begin
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`ifdef DEBUG
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$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
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`endif
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if (ENABLE_ILLINSTR_IRQ && irq_mask[2] && !irq_active) begin
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irq_pending[2] <= 1;
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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end else
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cpu_state <= cpu_state_trap;
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@ -645,6 +650,7 @@ module picorv32 #(
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cpu_state <= cpu_state_fetch;
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end else
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if (ENABLE_IRQ && instr_retirq) begin
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eoi <= 0;
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irq_active <= 0;
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latched_branch <= 1;
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latched_store <= 1;
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@ -652,10 +658,12 @@ module picorv32 #(
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cpu_state <= cpu_state_fetch;
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end else
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if (ENABLE_IRQ && instr_maskirq) begin
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irq_mask = decoded_rs2;
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latched_store <= 1;
|
||||
reg_out <= irq_mask;
|
||||
irq_mask <= (decoded_rs1 ? cpuregs[decoded_rs1] : 0) | MASKED_IRQ;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else
|
||||
if (ENABLE_TIMER_IRQ && instr_timer) begin
|
||||
if (ENABLE_IRQ && instr_timer) begin
|
||||
timer <= cpuregs[decoded_rs1];
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else begin
|
||||
|
|
@ -806,12 +814,18 @@ module picorv32 #(
|
|||
`ifdef DEBUG
|
||||
$display("MISALIGNED WORD: 0x%08x", reg_op1);
|
||||
`endif
|
||||
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
|
||||
next_irq_pending[irq_buserror] = 1;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end
|
||||
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
|
||||
`ifdef DEBUG
|
||||
$display("MISALIGNED HALFWORD: 0x%08x", reg_op1);
|
||||
`endif
|
||||
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
|
||||
next_irq_pending[irq_buserror] = 1;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end
|
||||
end
|
||||
|
|
@ -819,6 +833,9 @@ module picorv32 #(
|
|||
`ifdef DEBUG
|
||||
$display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);
|
||||
`endif
|
||||
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
|
||||
next_irq_pending[irq_buserror] = 1;
|
||||
end else
|
||||
cpu_state <= cpu_state_trap;
|
||||
end
|
||||
|
||||
|
|
@ -836,6 +853,8 @@ module picorv32 #(
|
|||
if (set_mem_do_wdata)
|
||||
mem_do_wdata <= 1;
|
||||
|
||||
irq_pending <= next_irq_pending & ~MASKED_IRQ;
|
||||
|
||||
reg_pc[1:0] <= 0;
|
||||
reg_next_pc[1:0] <= 0;
|
||||
current_pc = 'bx;
|
||||
|
|
@ -848,14 +867,15 @@ endmodule
|
|||
***************************************************************/
|
||||
|
||||
module picorv32_axi #(
|
||||
parameter ENABLE_COUNTERS = 1,
|
||||
parameter ENABLE_REGS_16_31 = 1,
|
||||
parameter ENABLE_REGS_DUALPORT = 1,
|
||||
parameter ENABLE_EXTERNAL_IRQ = 0,
|
||||
parameter ENABLE_ILLINSTR_IRQ = 0,
|
||||
parameter ENABLE_TIMER_IRQ = 0
|
||||
parameter [ 0:0] ENABLE_COUNTERS = 1,
|
||||
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
|
||||
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
|
||||
parameter [ 0:0] ENABLE_IRQ = 0,
|
||||
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
|
||||
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
|
||||
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010
|
||||
) (
|
||||
input clk, resetn, irq,
|
||||
input clk, resetn,
|
||||
output trap,
|
||||
|
||||
// AXI4-lite master memory interface
|
||||
|
|
@ -880,7 +900,11 @@ module picorv32_axi #(
|
|||
|
||||
input mem_axi_rvalid,
|
||||
output mem_axi_rready,
|
||||
input [31:0] mem_axi_rdata
|
||||
input [31:0] mem_axi_rdata,
|
||||
|
||||
// IRQ interface
|
||||
input [31:0] irq,
|
||||
output [31:0] eoi
|
||||
);
|
||||
wire mem_valid;
|
||||
wire [31:0] mem_addr;
|
||||
|
|
@ -923,13 +947,13 @@ module picorv32_axi #(
|
|||
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
|
||||
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
|
||||
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
|
||||
.ENABLE_EXTERNAL_IRQ (ENABLE_EXTERNAL_IRQ ),
|
||||
.ENABLE_ILLINSTR_IRQ (ENABLE_ILLINSTR_IRQ ),
|
||||
.ENABLE_TIMER_IRQ (ENABLE_TIMER_IRQ )
|
||||
.ENABLE_IRQ (ENABLE_IRQ ),
|
||||
.MASKED_IRQ (MASKED_IRQ ),
|
||||
.PROGADDR_RESET (PROGADDR_RESET ),
|
||||
.PROGADDR_IRQ (PROGADDR_IRQ )
|
||||
) picorv32_core (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
.irq (irq ),
|
||||
.trap (trap ),
|
||||
.mem_valid(mem_valid),
|
||||
.mem_addr (mem_addr ),
|
||||
|
|
@ -937,7 +961,9 @@ module picorv32_axi #(
|
|||
.mem_wstrb(mem_wstrb),
|
||||
.mem_instr(mem_instr),
|
||||
.mem_ready(mem_ready),
|
||||
.mem_rdata(mem_rdata)
|
||||
.mem_rdata(mem_rdata),
|
||||
.irq (irq ),
|
||||
.eoi (eoi )
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
16
testbench.v
16
testbench.v
|
|
@ -6,9 +6,15 @@ module testbench;
|
|||
|
||||
reg clk = 1;
|
||||
reg resetn = 0;
|
||||
wire irq = &uut.picorv32_core.count_cycle[12:0];
|
||||
reg [31:0] irq;
|
||||
wire trap;
|
||||
|
||||
always @* begin
|
||||
irq = 0;
|
||||
irq[4] = &uut.picorv32_core.count_cycle[12:0];
|
||||
irq[5] = &uut.picorv32_core.count_cycle[15:0];
|
||||
end
|
||||
|
||||
always #5 clk = ~clk;
|
||||
|
||||
initial begin
|
||||
|
|
@ -39,13 +45,10 @@ module testbench;
|
|||
reg [31:0] mem_axi_rdata;
|
||||
|
||||
picorv32_axi #(
|
||||
.ENABLE_EXTERNAL_IRQ (1),
|
||||
.ENABLE_ILLINSTR_IRQ (1),
|
||||
.ENABLE_TIMER_IRQ (1)
|
||||
.ENABLE_IRQ(1)
|
||||
) uut (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
.irq (irq ),
|
||||
.trap (trap ),
|
||||
.mem_axi_awvalid(mem_axi_awvalid),
|
||||
.mem_axi_awready(mem_axi_awready),
|
||||
|
|
@ -63,7 +66,8 @@ module testbench;
|
|||
.mem_axi_arprot (mem_axi_arprot ),
|
||||
.mem_axi_rvalid (mem_axi_rvalid ),
|
||||
.mem_axi_rready (mem_axi_rready ),
|
||||
.mem_axi_rdata (mem_axi_rdata )
|
||||
.mem_axi_rdata (mem_axi_rdata ),
|
||||
.irq (irq )
|
||||
);
|
||||
|
||||
reg [31:0] memory [0:64*1024/4-1];
|
||||
|
|
|
|||
Loading…
Reference in New Issue