Using Verilator in torture test bench

This commit is contained in:
Clifford Wolf 2016-04-10 12:35:16 +02:00
parent bc85a4c110
commit 9a5d35c195
4 changed files with 46 additions and 14 deletions

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@ -2,6 +2,7 @@
riscv-fesvr riscv-fesvr
riscv-isa-sim riscv-isa-sim
riscv-torture riscv-torture
obj_dir
tests tests
test.S test.S
test.elf test.elf

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@ -1,4 +1,10 @@
# Icarus Verilog
#TESTBENCH_EXE = tests/testbench.vvp
# Verilator
TESTBENCH_EXE = obj_dir/Vtestbench
test: riscv-torture/build.ok riscv-isa-sim/build.ok test: riscv-torture/build.ok riscv-isa-sim/build.ok
bash test.sh bash test.sh
@ -28,6 +34,10 @@ batch_list = $(shell bash -c 'for i in {0..999}; do printf "%03d\n" $$i; done')
batch: $(addprefix tests/test_,$(addsuffix .ok,$(batch_list))) batch: $(addprefix tests/test_,$(addsuffix .ok,$(batch_list)))
obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v
verilator --exe -Wno-fatal --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
$(MAKE) -C obj_dir -f Vtestbench.mk
tests/testbench.vvp: testbench.v ../../picorv32.v tests/testbench.vvp: testbench.v ../../picorv32.v
mkdir -p tests mkdir -p tests
iverilog -o tests/testbench.vvp testbench.v ../../picorv32.v iverilog -o tests/testbench.vvp testbench.v ../../picorv32.v
@ -55,8 +65,8 @@ tests/test_$(1).hex: tests/test_$(1).bin
tests/test_$(1).ref: tests/test_$(1).elf riscv-isa-sim/build.ok tests/test_$(1).ref: tests/test_$(1).elf riscv-isa-sim/build.ok
LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike tests/test_$(1).elf > tests/test_$(1).ref LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike tests/test_$(1).elf > tests/test_$(1).ref
tests/test_$(1).ok: tests/testbench.vvp tests/test_$(1).hex tests/test_$(1).ref tests/test_$(1).ok: $(TESTBENCH_EXE) tests/test_$(1).hex tests/test_$(1).ref
vvp tests/testbench.vvp +hex=tests/test_$(1).hex +ref=tests/test_$(1).ref | tee tests/test_$(1).out $(TESTBENCH_EXE) +hex=tests/test_$(1).hex +ref=tests/test_$(1).ref | tee tests/test_$(1).out
grep -q PASSED tests/test_$(1).out grep -q PASSED tests/test_$(1).out
mv tests/test_$(1).out tests/test_$(1).ok mv tests/test_$(1).out tests/test_$(1).ok
endef endef
@ -71,7 +81,7 @@ loop:
done done
clean: clean:
rm -rf riscv-torture riscv-fesvr riscv-isa-sim tests rm -rf riscv-torture riscv-fesvr riscv-isa-sim tests obj_dir
rm -f test.S test.elf test.bin test.hex test.ref test.vvp rm -f test.S test.elf test.bin test.hex test.ref test.vvp
.PHONY: test batch loop clean .PHONY: test batch loop clean

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@ -0,0 +1,18 @@
#include "Vtestbench.h"
#include "verilated.h"
int main(int argc, char **argv, char **env)
{
Verilated::commandArgs(argc, argv);
Vtestbench* top = new Vtestbench;
top->clk = 0;
while (!Verilated::gotFinish()) {
top->clk = !top->clk;
top->eval();
}
delete top;
exit(0);
}

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@ -33,25 +33,20 @@ module testbench (
.mem_rdata (mem_rdata ) .mem_rdata (mem_rdata )
); );
reg [1023:0] hex_filename; localparam integer filename_len = 18;
reg [1023:0] ref_filename; reg [8*filename_len-1:0] hex_filename;
reg [8*filename_len-1:0] ref_filename;
reg [31:0] memory [0:4095]; reg [31:0] memory [0:4095];
reg [31:0] memory_ref [0:4095]; reg [31:0] memory_ref [0:4095];
integer i, errcount; integer i, errcount;
integer cycle = 0;
initial begin initial begin
if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory); if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory);
if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref); if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref);
// $dumpfile("testbench.vcd"); // $dumpfile("testbench.vcd");
// $dumpvars(0, testbench); // $dumpvars(0, testbench);
repeat (10) @(posedge clk);
resetn <= 1;
repeat (100000) @(posedge clk);
$display("FAILED: Timeout!");
$finish;
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -79,10 +74,18 @@ module testbench (
end end
end end
if (errcount) if (errcount)
$display("FAILED: Got %1d errors for %1s => %1s!", errcount, hex_filename, ref_filename); $display("FAILED: Got %1d errors for %s => %s!", errcount, hex_filename, ref_filename);
else else
$display("PASSED %1s => %1s.", hex_filename, ref_filename); $display("PASSED %s => %s.", hex_filename, ref_filename);
$finish; $finish;
end end
if (cycle > 100000) begin
$display("FAILED: Timeout!");
$finish;
end
resetn <= cycle > 10;
cycle <= cycle + 1;
end end
endmodule endmodule