diff --git a/picorv32.v b/picorv32.v
index 50fdd78..d65c1bc 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -51,16 +51,10 @@
  ***************************************************************/
 
 module picorv32 #(
-	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
-	parameter [ 0:0] LATCHED_MEM_RDATA = 0,
 	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
 	parameter [ 0:0] BARREL_SHIFTER = 0,
 	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
 	parameter [ 0:0] TWO_CYCLE_ALU = 0,
-	parameter [ 0:0] ENABLE_PCPI = 0,
-	parameter [ 0:0] ENABLE_MUL = 0,
-	parameter [ 0:0] ENABLE_FAST_MUL = 0,
-	parameter [ 0:0] ENABLE_DIV = 0,
 	parameter [ 0:0] ENABLE_IRQ = 0,
 	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
 	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
@@ -112,11 +106,11 @@ module picorv32 #(
 	localparam integer irq_ebreak = 1;
 	localparam integer irq_buserror = 2;
 
-	localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
-	localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
-	localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
+	localparam integer irqregs_offset = 32;
+	localparam integer regfile_size = 32 + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
+	localparam integer regindex_bits = 5 + ENABLE_IRQ*ENABLE_IRQ_QREGS;
 
-	localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
+	localparam WITH_PCPI = 1; // AAAA
 
 	localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
 	localparam [35:0] TRACE_ADDR   = {4'b 0010, 32'b 0};
@@ -176,76 +170,50 @@ module picorv32 #(
 	reg        pcpi_int_wait;
 	reg        pcpi_int_ready;
 
-	generate if (ENABLE_FAST_MUL) begin
-		picorv32_pcpi_fast_mul pcpi_mul (
-			.clk       (clk            ),
-			.resetn    (resetn         ),
-			.pcpi_valid(pcpi_valid     ),
-			.pcpi_insn (pcpi_insn      ),
-			.pcpi_rs1  (pcpi_rs1       ),
-			.pcpi_rs2  (pcpi_rs2       ),
-			.pcpi_wr   (pcpi_mul_wr    ),
-			.pcpi_rd   (pcpi_mul_rd    ),
-			.pcpi_wait (pcpi_mul_wait  ),
-			.pcpi_ready(pcpi_mul_ready )
-		);
-	end else if (ENABLE_MUL) begin
-		picorv32_pcpi_mul pcpi_mul (
-			.clk       (clk            ),
-			.resetn    (resetn         ),
-			.pcpi_valid(pcpi_valid     ),
-			.pcpi_insn (pcpi_insn      ),
-			.pcpi_rs1  (pcpi_rs1       ),
-			.pcpi_rs2  (pcpi_rs2       ),
-			.pcpi_wr   (pcpi_mul_wr    ),
-			.pcpi_rd   (pcpi_mul_rd    ),
-			.pcpi_wait (pcpi_mul_wait  ),
-			.pcpi_ready(pcpi_mul_ready )
-		);
-	end else begin
-		assign pcpi_mul_wr = 0;
-		assign pcpi_mul_rd = 32'bx;
-		assign pcpi_mul_wait = 0;
-		assign pcpi_mul_ready = 0;
-	end endgenerate
 
-	generate if (ENABLE_DIV) begin
-		picorv32_pcpi_div pcpi_div (
-			.clk       (clk            ),
-			.resetn    (resetn         ),
-			.pcpi_valid(pcpi_valid     ),
-			.pcpi_insn (pcpi_insn      ),
-			.pcpi_rs1  (pcpi_rs1       ),
-			.pcpi_rs2  (pcpi_rs2       ),
-			.pcpi_wr   (pcpi_div_wr    ),
-			.pcpi_rd   (pcpi_div_rd    ),
-			.pcpi_wait (pcpi_div_wait  ),
-			.pcpi_ready(pcpi_div_ready )
-		);
-	end else begin
-		assign pcpi_div_wr = 0;
-		assign pcpi_div_rd = 32'bx;
-		assign pcpi_div_wait = 0;
-		assign pcpi_div_ready = 0;
-	end endgenerate
+	picorv32_pcpi_mul pcpi_mul (
+		.clk       (clk            ),
+		.resetn    (resetn         ),
+		.pcpi_valid(pcpi_valid     ),
+		.pcpi_insn (pcpi_insn      ),
+		.pcpi_rs1  (pcpi_rs1       ),
+		.pcpi_rs2  (pcpi_rs2       ),
+		.pcpi_wr   (pcpi_mul_wr    ),
+		.pcpi_rd   (pcpi_mul_rd    ),
+		.pcpi_wait (pcpi_mul_wait  ),
+		.pcpi_ready(pcpi_mul_ready )
+	);
+
+	picorv32_pcpi_div pcpi_div (
+		.clk       (clk            ),
+		.resetn    (resetn         ),
+		.pcpi_valid(pcpi_valid     ),
+		.pcpi_insn (pcpi_insn      ),
+		.pcpi_rs1  (pcpi_rs1       ),
+		.pcpi_rs2  (pcpi_rs2       ),
+		.pcpi_wr   (pcpi_div_wr    ),
+		.pcpi_rd   (pcpi_div_rd    ),
+		.pcpi_wait (pcpi_div_wait  ),
+		.pcpi_ready(pcpi_div_ready )
+	);
 
 	always @* begin
 		pcpi_int_wr = 0;
 		pcpi_int_rd = 32'bx;
-		pcpi_int_wait  = |{ENABLE_PCPI && pcpi_wait,  (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait,  ENABLE_DIV && pcpi_div_wait};
-		pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
+		pcpi_int_wait  = |{pcpi_mul_wait, pcpi_div_wait};
+		pcpi_int_ready = |{pcpi_mul_ready, pcpi_div_ready};
 
 		(* parallel_case *)
 		case (1'b1)
-			ENABLE_PCPI && pcpi_ready: begin
-				pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
-				pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
+			0: begin
+				pcpi_int_wr = 0;
+				pcpi_int_rd = 0;
 			end
-			(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
+			pcpi_mul_ready: begin
 				pcpi_int_wr = pcpi_mul_wr;
 				pcpi_int_rd = pcpi_mul_rd;
 			end
-			ENABLE_DIV && pcpi_div_ready: begin
+			pcpi_div_ready: begin
 				pcpi_int_wr = pcpi_div_wr;
 				pcpi_int_rd = pcpi_div_rd;
 			end
@@ -281,7 +249,7 @@ module picorv32 #(
 	assign mem_la_read = resetn && ((!mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)));
 	assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2], 2'b00} : {reg_op1[31:2], 2'b00};
 
-	assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
+	assign mem_rdata_latched_noshuffle = mem_xfer ? mem_rdata : mem_rdata_q;
 
 	assign mem_rdata_latched = mem_rdata_latched_noshuffle;
 
diff --git a/testbench_wb.v b/testbench_wb.v
index b6e991d..ff5c1f5 100644
--- a/testbench_wb.v
+++ b/testbench_wb.v
@@ -191,8 +191,6 @@ module picorv32_wb #(
   assign resetn = ~wb_rst_i;
 
   picorv32 #(
-      .ENABLE_MUL(1),
-      .ENABLE_DIV(1),
       .ENABLE_IRQ(1),
       .ENABLE_TRACE(1),
       .MASKED_IRQ(32'h0000_0000),