colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Towards compressed ISA support

This commit is contained in:
Clifford Wolf 2015-11-19 04:02:00 +01:00
parent c4e711209c
commit 9d5f8ad8e6
2 changed files with 36 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
firmware/irq.c
View File

@ -31,7 +31,8 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs)
if ((irqs & 6) != 0) if ((irqs & 6) != 0)
{ {
uint32_t pc = regs[0] - 4; uint32_t pc = regs[0] - 4;
uint32_t instr = *(uint32_t*)pc; uint16_t *instr_hwords = (uint16_t*)pc;
uint32_t instr = instr_hwords[0] | (instr_hwords[1] << 16);
print_str("\n"); print_str("\n");
print_str("------------------------------------------------------------\n"); print_str("------------------------------------------------------------\n");

36
picorv32.v
View File

@ -237,6 +237,10 @@ module picorv32 #(
case (mem_rdata_latched[1:0]) case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0 2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13]) case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= {mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6]};
end
3'b 110: begin // C.SW 3'b 110: begin // C.SW
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010; mem_rdata_q[14:12] <= 3'b 010;
@ -262,15 +266,21 @@ module picorv32 #(
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end end
end end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
end
3'b 110: begin // C.BEQZ 3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000; mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:15], mem_rdata_q[11:8] } <= { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end end
3'b 111: begin // C.BNEZ 3'b 111: begin // C.BNEZ
mem_rdata_q[14:12] <= 3'b001; mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:15], mem_rdata_q[11:8] } <= { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end end
@ -295,6 +305,10 @@ module picorv32 #(
mem_rdata_q[14:12] <= 3'b000; mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0; mem_rdata_q[31:20] <= 12'b0;
end end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end end
3'b110: begin // C.SWSP 3'b110: begin // C.SWSP
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
@ -525,6 +539,11 @@ module picorv32 #(
case (mem_rdata_latched[1:0]) case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0 2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13]) case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
is_alu_reg_imm <= |mem_rdata_latched[12:5];
decoded_rs1 <= 2;
decoded_rd <= 8 + mem_rdata_latched[9:7];
end
3'b110: begin // C.SW 3'b110: begin // C.SW
is_sb_sh_sw <= 1; is_sb_sh_sw <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7]; decoded_rs1 <= 8 + mem_rdata_latched[9:7];
@ -559,6 +578,13 @@ module picorv32 #(
decoded_rs1 <= 0; decoded_rs1 <= 0;
end end
end end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
end
3'b101: begin // C.J 3'b101: begin // C.J
instr_jal <= 1; instr_jal <= 1;
end end
@ -598,6 +624,12 @@ module picorv32 #(
decoded_rd <= 1; decoded_rd <= 1;
decoded_rs1 <= mem_rdata_latched[11:7]; decoded_rs1 <= mem_rdata_latched[11:7];
end end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= mem_rdata_latched[6:2];
end
end end
3'b110: begin // C.SWSP 3'b110: begin // C.SWSP
is_sb_sh_sw <= 1; is_sb_sh_sw <= 1;