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Added cpu?_trap signals to tracecmp3.v

This commit is contained in:
Clifford Wolf 2016-12-03 12:48:00 +01:00
parent 9c494af6e1
commit 9d6fdda1fa
1 changed files with 4 additions and 0 deletions
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4
scripts/smtbmc/tracecmp3.v
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@ -15,6 +15,7 @@ module testbench (
always @(posedge clk) always @(posedge clk)
resetn <= 1; resetn <= 1;
wire cpu0_trap;
wire cpu0_mem_valid; wire cpu0_mem_valid;
wire cpu0_mem_instr; wire cpu0_mem_instr;
wire cpu0_mem_ready; wire cpu0_mem_ready;
@ -25,6 +26,7 @@ module testbench (
wire cpu0_trace_valid; wire cpu0_trace_valid;
wire [35:0] cpu0_trace_data; wire [35:0] cpu0_trace_data;
wire cpu1_trap;
wire cpu1_mem_valid; wire cpu1_mem_valid;
wire cpu1_mem_instr; wire cpu1_mem_instr;
wire cpu1_mem_ready; wire cpu1_mem_ready;
@ -91,6 +93,7 @@ module testbench (
) cpu0 ( ) cpu0 (
.clk (clk ), .clk (clk ),
.resetn (resetn ), .resetn (resetn ),
.trap (cpu0_trap ),
.mem_valid (cpu0_mem_valid ), .mem_valid (cpu0_mem_valid ),
.mem_instr (cpu0_mem_instr ), .mem_instr (cpu0_mem_instr ),
.mem_ready (cpu0_mem_ready ), .mem_ready (cpu0_mem_ready ),
@ -118,6 +121,7 @@ module testbench (
) cpu1 ( ) cpu1 (
.clk (clk ), .clk (clk ),
.resetn (resetn ), .resetn (resetn ),
.trap (cpu1_trap ),
.mem_valid (cpu1_mem_valid ), .mem_valid (cpu1_mem_valid ),
.mem_instr (cpu1_mem_instr ), .mem_instr (cpu1_mem_instr ),
.mem_ready (cpu1_mem_ready ), .mem_ready (cpu1_mem_ready ),