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Merge branch 'master' into compressed

This commit is contained in:
Clifford Wolf 2015-12-16 15:45:12 +01:00
parent 5953e57899 6e6aeaeab6
commit 9fa0890bd1
4 changed files with 56 additions and 129 deletions
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4
README.md
View File

@ -531,7 +531,7 @@ pure RV32I target, and install it in `/opt/riscv32i`:
git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
cd riscv-gnu-toolchain-rv32i cd riscv-gnu-toolchain-rv32i
git checkout b68866f git checkout 4bcd4f5
mkdir build; cd build mkdir build; cd build
../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i ../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i
@ -541,7 +541,7 @@ The commands will all be named using the prefix `riscv32-unknown-elf-`, which
makes it easy to install them side-by-side with the regular riscv-tools, which makes it easy to install them side-by-side with the regular riscv-tools, which
are using the name prefix `riscv64-unknown-elf-` by default. are using the name prefix `riscv64-unknown-elf-` by default.
*Note: This instructions are for git rev b68866f (2015-11-09) of riscv-gnu-toolchain.* *Note: This instructions are for git rev 4bcd4f5 (2015-12-14) of riscv-gnu-toolchain.*
Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs

50
scripts/cxxdemo/firmware.cc
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@ -3,12 +3,62 @@
#include <vector> #include <vector>
#include <algorithm> #include <algorithm>
class ExampleBaseClass
{
public:
ExampleBaseClass() {
std::cout << "ExampleBaseClass()" << std::endl;
}
virtual ~ExampleBaseClass() {
std::cout << "~ExampleBaseClass()" << std::endl;
}
virtual void print_something_virt() {
std::cout << "ExampleBaseClass::print_something_virt()" << std::endl;
}
void print_something_novirt() {
std::cout << "ExampleBaseClass::print_something_novirt()" << std::endl;
}
};
class ExampleSubClass : public ExampleBaseClass
{
public:
ExampleSubClass() {
std::cout << "ExampleSubClass()" << std::endl;
}
virtual ~ExampleSubClass() {
std::cout << "~ExampleSubClass()" << std::endl;
}
virtual void print_something_virt() {
std::cout << "ExampleSubClass::print_something_virt()" << std::endl;
}
void print_something_novirt() {
std::cout << "ExampleSubClass::print_something_novirt()" << std::endl;
}
};
int main() int main()
{ {
printf("Hello World, C!\n"); printf("Hello World, C!\n");
std::cout << "Hello World, C++!" << std::endl; std::cout << "Hello World, C++!" << std::endl;
ExampleBaseClass *obj = new ExampleBaseClass;
obj->print_something_virt();
obj->print_something_novirt();
delete obj;
obj = new ExampleSubClass;
obj->print_something_virt();
obj->print_something_novirt();
delete obj;
std::vector<unsigned int> some_ints; std::vector<unsigned int> some_ints;
some_ints.push_back(0x48c9b3e4); some_ints.push_back(0x48c9b3e4);
some_ints.push_back(0x79109b6a); some_ints.push_back(0x79109b6a);

4
tests/srli.S
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@ -48,11 +48,11 @@ RVTEST_CODE_BEGIN
TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 ); TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 ); TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_IMM_ZEROSRC1( 28, srli, 0, 31 ); TEST_IMM_ZEROSRC1( 28, srli, 0, 31 );
TEST_IMM_ZERODEST( 29, srli, 33, 20 ); TEST_IMM_ZERODEST( 29, srli, 33, 20 );

127
tests/test_macros.h
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@ -286,7 +286,7 @@ test_ ## testnum: \
test_ ## testnum: \ test_ ## testnum: \
li TESTNUM, testnum; \ li TESTNUM, testnum; \
li x4, 0; \ li x4, 0; \
1: la x1, result; \ 1: li x1, result; \
TEST_INSERT_NOPS_ ## src1_nops \ TEST_INSERT_NOPS_ ## src1_nops \
la x2, base; \ la x2, base; \
TEST_INSERT_NOPS_ ## src2_nops \ TEST_INSERT_NOPS_ ## src2_nops \
@ -304,7 +304,7 @@ test_ ## testnum: \
li x4, 0; \ li x4, 0; \
1: la x2, base; \ 1: la x2, base; \
TEST_INSERT_NOPS_ ## src1_nops \ TEST_INSERT_NOPS_ ## src1_nops \
la x1, result; \ li x1, result; \
TEST_INSERT_NOPS_ ## src2_nops \ TEST_INSERT_NOPS_ ## src2_nops \
store_inst x1, offset(x2); \ store_inst x1, offset(x2); \
load_inst x3, offset(x2); \ load_inst x3, offset(x2); \
@ -564,129 +564,6 @@ test_ ## testnum: \
.double result; \ .double result; \
1: 1:
#-----------------------------------------------------------------------
# RV64SV MACROS
#-----------------------------------------------------------------------
#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
la a0, handler ## testnum; \
csrw stvec, a0; \
vsetcfg nxreg, nfreg; \
li a0, 4; \
vsetvl a0, a0; \
la a0, src1; \
la a1, src2; \
vld vx2, a0; \
vld vx3, a1; \
lui a0,%hi(vtcode1 ## testnum); \
vf %lo(vtcode1 ## testnum)(a0); \
la reg2, dest; \
illegal ## testnum: \
inst reg1, reg2; \
la a3, dest; \
vsd vx2, a3; \
fence; \
vtcode1 ## testnum: \
add x2, x2, x3; \
stop; \
vtcode2 ## testnum: \
add x2, x2, x3; \
stop; \
handler ## testnum: \
vxcptkill; \
li TESTNUM,2; \
csrr a0, scause; \
li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
bne a0,a1,fail; \
csrr a0, sbadaddr; \
la a1, illegal ## testnum; \
lw a2, 0(a1); \
bne a0, a2, fail; \
vsetcfg 32,0; \
li a0,4; \
vsetvl a0,a0; \
la a0,src1; \
la a1,src2; \
vld vx2,a0; \
vld vx3,a1; \
lui a0,%hi(vtcode2 ## testnum); \
vf %lo(vtcode2 ## testnum)(a0); \
la a3,dest; \
vsd vx2,a3; \
fence; \
ld a1,0(a3); \
li a2,5; \
li TESTNUM,2; \
bne a1,a2,fail; \
ld a1,8(a3); \
li TESTNUM,3; \
bne a1,a2,fail; \
ld a1,16(a3); \
li TESTNUM,4; \
bne a1,a2,fail; \
ld a1,24(a3); \
li TESTNUM,5; \
bne a1,a2,fail; \
#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
la a0, handler ## testnum; \
csrw stvec, a0; \
vsetcfg nxreg, nfreg; \
li a0, 4; \
vsetvl a0, a0; \
la a0, src1; \
la a1, src2; \
vld vx2, a0; \
vld vx3, a1; \
lui a0,%hi(vtcode1 ## testnum); \
vf %lo(vtcode1 ## testnum)(a0); \
la a3, dest; \
vsd vx2, a3; \
fence; \
vtcode1 ## testnum: \
add x2, x2, x3; \
illegal ## testnum: \
inst reg1, reg2, reg3; \
stop; \
vtcode2 ## testnum: \
add x2, x2, x3; \
stop; \
handler ## testnum: \
vxcptkill; \
li TESTNUM,2; \
csrr a0, scause; \
li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
bne a0,a1,fail; \
csrr a0, sbadaddr; \
la a1,illegal ## testnum; \
bne a0,a1,fail; \
vsetcfg 32,0; \
li a0,4; \
vsetvl a0,a0; \
la a0,src1; \
la a1,src2; \
vld vx2,a0; \
vld vx3,a1; \
lui a0,%hi(vtcode2 ## testnum); \
vf %lo(vtcode2 ## testnum)(a0); \
la a3,dest; \
vsd vx2,a3; \
fence; \
ld a1,0(a3); \
li a2,5; \
li TESTNUM,2; \
bne a1,a2,fail; \
ld a1,8(a3); \
li TESTNUM,3; \
bne a1,a2,fail; \
ld a1,16(a3); \
li TESTNUM,4; \
bne a1,a2,fail; \
ld a1,24(a3); \
li TESTNUM,5; \
bne a1,a2,fail; \
#----------------------------------------------------------------------- #-----------------------------------------------------------------------
# Pass and fail code (assumes test num is in TESTNUM) # Pass and fail code (assumes test num is in TESTNUM)
#----------------------------------------------------------------------- #-----------------------------------------------------------------------