Rename RVFI ports
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e9b6bcf9c0
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picorv32.v
44
picorv32.v
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@ -105,16 +105,16 @@ module picorv32 #(
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`ifdef RISCV_FORMAL
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output reg rvfi_valid,
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output reg [ 7:0] rvfi_order,
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output reg [ 4:0] rvfi_rs1,
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output reg [ 4:0] rvfi_rs2,
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output reg [ 4:0] rvfi_rd,
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output reg [31:0] rvfi_insn,
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output reg [31:0] rvfi_pre_pc,
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output reg [31:0] rvfi_pre_rs1,
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output reg [31:0] rvfi_pre_rs2,
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output reg [31:0] rvfi_post_pc,
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output reg [31:0] rvfi_post_rd,
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output reg rvfi_post_trap,
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output reg rvfi_trap,
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output reg [ 4:0] rvfi_rs1_addr,
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output reg [ 4:0] rvfi_rs2_addr,
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output reg [31:0] rvfi_rs1_rdata,
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output reg [31:0] rvfi_rs2_rdata,
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output reg [ 4:0] rvfi_rd_addr,
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output reg [31:0] rvfi_rd_wdata,
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output reg [31:0] rvfi_pc_rdata,
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output reg [31:0] rvfi_pc_wdata,
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output reg [31:0] rvfi_mem_addr,
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output reg [ 3:0] rvfi_mem_rmask,
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output reg [ 3:0] rvfi_mem_wmask,
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@ -1874,24 +1874,24 @@ module picorv32 #(
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rvfi_order <= 0;
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rvfi_insn <= dbg_insn_opcode;
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rvfi_rs1 <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs2 <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
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rvfi_pre_pc <= dbg_insn_addr;
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rvfi_pre_rs1 <= dbg_rs1val_valid ? dbg_rs1val : 0;
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rvfi_pre_rs2 <= dbg_rs2val_valid ? dbg_rs2val : 0;
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rvfi_post_trap <= trap;
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rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
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rvfi_pc_rdata <= dbg_insn_addr;
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rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
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rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
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rvfi_trap <= trap;
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if (!resetn) begin
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rvfi_rd <= 0;
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rvfi_post_rd <= 0;
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rvfi_rd_addr <= 0;
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rvfi_rd_wdata <= 0;
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end else
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if (cpuregs_write) begin
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rvfi_rd <= latched_rd;
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rvfi_post_rd <= latched_rd ? cpuregs_wrdata : 0;
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rvfi_rd_addr <= latched_rd;
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rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
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end else
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if (rvfi_valid) begin
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rvfi_rd <= 0;
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rvfi_post_rd <= 0;
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rvfi_rd_addr <= 0;
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rvfi_rd_wdata <= 0;
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end
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if (dbg_mem_valid && dbg_mem_ready) begin
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@ -1912,7 +1912,7 @@ module picorv32 #(
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end
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always @* begin
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rvfi_post_pc = dbg_insn_addr;
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rvfi_pc_wdata = dbg_insn_addr;
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end
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`endif
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