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Being more aggressive with parallel cases

This commit is contained in:
Clifford Wolf 2015-07-02 12:55:05 +02:00
parent c10125eb5c
commit ab503d5756
1 changed files with 177 additions and 149 deletions
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98
picorv32.v
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@ -639,26 +639,29 @@ module picorv32 #(
current_pc = reg_next_pc; current_pc = reg_next_pc;
if (latched_branch) begin (* parallel_case *)
case (1'b1)
latched_branch: begin
current_pc = latched_store ? (latched_stalu ? reg_alu_out : reg_out) : reg_next_pc; current_pc = latched_store ? (latched_stalu ? reg_alu_out : reg_out) : reg_next_pc;
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);) `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);)
cpuregs[latched_rd] <= reg_pc + 4; cpuregs[latched_rd] <= reg_pc + 4;
end else end
if (latched_store) begin latched_store && !latched_branch: begin
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? reg_alu_out : reg_out);) `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? reg_alu_out : reg_out);)
cpuregs[latched_rd] <= latched_stalu ? reg_alu_out : reg_out; cpuregs[latched_rd] <= latched_stalu ? reg_alu_out : reg_out;
end else end
if (ENABLE_IRQ && irq_state[0]) begin ENABLE_IRQ && irq_state[0]: begin
cpuregs[latched_rd] <= current_pc; cpuregs[latched_rd] <= current_pc;
current_pc = PROGADDR_IRQ; current_pc = PROGADDR_IRQ;
irq_active <= 1; irq_active <= 1;
mem_do_rinst <= 1; mem_do_rinst <= 1;
end else end
if (ENABLE_IRQ && irq_state[1]) begin ENABLE_IRQ && irq_state[1]: begin
eoi <= irq_pending & ~irq_mask; eoi <= irq_pending & ~irq_mask;
cpuregs[latched_rd] <= irq_pending & ~irq_mask; cpuregs[latched_rd] <= irq_pending & ~irq_mask;
next_irq_pending = next_irq_pending & irq_mask; next_irq_pending = next_irq_pending & irq_mask;
end end
endcase
reg_pc <= current_pc; reg_pc <= current_pc;
reg_next_pc <= current_pc; reg_next_pc <= current_pc;
@ -711,7 +714,10 @@ module picorv32 #(
reg_op1 <= 'bx; reg_op1 <= 'bx;
reg_op2 <= 'bx; reg_op2 <= 'bx;
`debug($display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");) `debug($display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");)
if ((CATCH_ILLINSN || WITH_PCPI) && instr_trap) begin
(* parallel_case *)
case (1'b1)
(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
if (WITH_PCPI) begin if (WITH_PCPI) begin
reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0; reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
if (ENABLE_REGS_DUALPORT) begin if (ENABLE_REGS_DUALPORT) begin
@ -744,8 +750,8 @@ module picorv32 #(
end else end else
cpu_state <= cpu_state_trap; cpu_state <= cpu_state_trap;
end end
end else end
if (is_rdcycle_rdcycleh_rdinstr_rdinstrh) begin ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *) (* parallel_case, full_case *)
case (1'b1) case (1'b1)
instr_rdcycle: instr_rdcycle:
@ -759,79 +765,98 @@ module picorv32 #(
endcase endcase
latched_store <= 1; latched_store <= 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end
if (is_lui_auipc_jal) begin is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc; reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm; reg_op2 <= decoded_imm;
mem_do_rinst <= mem_do_prefetch; mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end else end
if (ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq) begin ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
reg_out <= cpuregs[decoded_rs1]; reg_out <= cpuregs[decoded_rs1];
latched_store <= 1; latched_store <= 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end
if (ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq) begin ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
reg_out <= cpuregs[decoded_rs1]; reg_out <= cpuregs[decoded_rs1];
latched_rd <= latched_rd | irqregs_offset; latched_rd <= latched_rd | irqregs_offset;
latched_store <= 1; latched_store <= 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end
if (ENABLE_IRQ && instr_retirq) begin ENABLE_IRQ && instr_retirq: begin
eoi <= 0; eoi <= 0;
irq_active <= 0; irq_active <= 0;
latched_branch <= 1; latched_branch <= 1;
latched_store <= 1; latched_store <= 1;
reg_out <= cpuregs[decoded_rs1]; reg_out <= cpuregs[decoded_rs1];
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end
if (ENABLE_IRQ && instr_maskirq) begin ENABLE_IRQ && instr_maskirq: begin
latched_store <= 1; latched_store <= 1;
reg_out <= irq_mask; reg_out <= irq_mask;
irq_mask <= (decoded_rs1 ? cpuregs[decoded_rs1] : 0) | MASKED_IRQ; irq_mask <= (decoded_rs1 ? cpuregs[decoded_rs1] : 0) | MASKED_IRQ;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer) begin ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
latched_store <= 1; latched_store <= 1;
reg_out <= timer; reg_out <= timer;
timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0; timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else begin end
is_lb_lh_lw_lbu_lhu: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);) `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0; reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
if (is_lb_lh_lw_lbu_lhu) begin
cpu_state <= cpu_state_ldmem; cpu_state <= cpu_state_ldmem;
mem_do_rinst <= 1; mem_do_rinst <= 1;
end else if (is_slli_srli_srai) begin end
is_slli_srli_srai: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
reg_sh <= decoded_rs2; reg_sh <= decoded_rs2;
cpu_state <= cpu_state_shift; cpu_state <= cpu_state_shift;
end else if (is_jalr_addi_slti_sltiu_xori_ori_andi) begin end
is_jalr_addi_slti_sltiu_xori_ori_andi: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
reg_op2 <= decoded_imm; reg_op2 <= decoded_imm;
mem_do_rinst <= mem_do_prefetch; mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end else if (ENABLE_REGS_DUALPORT) begin end
default: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
if (ENABLE_REGS_DUALPORT) begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);) `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0; reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0; reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
if (is_sb_sh_sw) begin (* parallel_case *)
case (1'b1)
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem; cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1; mem_do_rinst <= 1;
end else if (is_sll_srl_sra) begin end
is_sll_srl_sra: begin
cpu_state <= cpu_state_shift; cpu_state <= cpu_state_shift;
end else begin end
default: begin
mem_do_rinst <= mem_do_prefetch; mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
endcase
end else end else
cpu_state <= cpu_state_ld_rs2; cpu_state <= cpu_state_ld_rs2;
end end
endcase
end end
cpu_state_ld_rs2: begin cpu_state_ld_rs2: begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);) `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0; reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0; reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
if (WITH_PCPI && instr_trap) begin
(* parallel_case *)
case (1'b1)
WITH_PCPI && instr_trap: begin
pcpi_valid <= 1; pcpi_valid <= 1;
if (pcpi_int_ready) begin if (pcpi_int_ready) begin
mem_do_rinst <= 1; mem_do_rinst <= 1;
@ -848,16 +873,19 @@ module picorv32 #(
end else end else
cpu_state <= cpu_state_trap; cpu_state <= cpu_state_trap;
end end
end else end
if (is_sb_sh_sw) begin is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem; cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1; mem_do_rinst <= 1;
end else if (is_sll_srl_sra) begin end
is_sll_srl_sra: begin
cpu_state <= cpu_state_shift; cpu_state <= cpu_state_shift;
end else begin end
default: begin
mem_do_rinst <= mem_do_prefetch; mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
endcase
end end
cpu_state_exec: begin cpu_state_exec: begin