Add PICORV32_REGS mechanism for ASIC sram instantiation
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Clifford Wolf
parent
500db14e44
commit
ad08edd2e5
68
picorv32.v
68
picorv32.v
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@ -42,6 +42,14 @@
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`define assert(assert_expr) empty_statement
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`endif
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// uncomment this for register file in extra module
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// `define PICORV32_REGS picorv32_regs
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// this macro can be used to check if the verilog files in your
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// design are read in the correct order.
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`define PICORV32_V
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/***************************************************************
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* picorv32
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***************************************************************/
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@ -149,7 +157,6 @@ module picorv32 #(
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reg [63:0] count_cycle, count_instr;
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reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
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reg [31:0] cpuregs [0:regfile_size-1];
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reg [4:0] reg_sh;
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reg [31:0] next_insn_opcode;
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@ -175,6 +182,9 @@ module picorv32 #(
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reg [31:0] irq_pending;
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reg [31:0] timer;
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`ifndef PICORV32_REGS
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reg [31:0] cpuregs [0:regfile_size-1];
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integer i;
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initial begin
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if (REGS_INIT_ZERO) begin
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@ -182,6 +192,7 @@ module picorv32 #(
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cpuregs[i] = 0;
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end
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end
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`endif
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task empty_statement;
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// This task is used by the `assert directive in non-formal mode to
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@ -1300,6 +1311,7 @@ module picorv32 #(
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end
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end
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`ifndef PICORV32_REGS
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always @(posedge clk) begin
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if (resetn && cpuregs_write && latched_rd)
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cpuregs[latched_rd] <= cpuregs_wrdata;
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@ -1325,6 +1337,37 @@ module picorv32 #(
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cpuregs_rs2 = cpuregs_rs1;
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end
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end
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`else
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wire[31:0] cpuregs_rdata1;
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wire[31:0] cpuregs_rdata2;
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wire [5:0] cpuregs_waddr = latched_rd;
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wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
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wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
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`PICORV32_REGS cpuregs (
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.clk(clk),
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.wen(resetn && cpuregs_write && latched_rd),
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.waddr(cpuregs_waddr),
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.raddr1(cpuregs_raddr1),
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.raddr2(cpuregs_raddr2),
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.wdata(cpuregs_wrdata),
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.rdata1(cpuregs_rdata1),
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.rdata2(cpuregs_rdata2)
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);
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always @* begin
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decoded_rs = 'bx;
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if (ENABLE_REGS_DUALPORT) begin
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cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
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cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
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end else begin
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decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
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cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
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cpuregs_rs2 = cpuregs_rs1;
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end
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end
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`endif
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assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
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@ -2051,6 +2094,29 @@ module picorv32 #(
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`endif
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endmodule
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// This is a simple example implementation of PICORV32_REGS.
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// Use the PICORV32_REGS mechanism if you want to use custom
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// memory resources to implement the processor register file.
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// Note that your implementation must match the requirements of
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// the PicoRV32 configuration. (e.g. QREGS, etc)
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module picorv32_regs (
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input clk, wen,
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input [5:0] waddr,
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input [5:0] raddr1,
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input [5:0] raddr2,
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input [31:0] wdata,
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output [31:0] rdata1,
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output [31:0] rdata2
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);
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reg [31:0] regs [0:30];
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always @(posedge clk)
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if (wen) regs[~waddr[4:0]] <= wdata;
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assign rdata1 = regs[~raddr1[4:0]];
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assign rdata2 = regs[~raddr2[4:0]];
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endmodule
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/***************************************************************
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* picorv32_pcpi_mul
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@ -12,3 +12,4 @@
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/hx8kdemo_syn_tb.vvp
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/hx8kdemo_tb.vvp
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/testbench.vcd
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/cmos.log
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@ -52,11 +52,16 @@ spiflash_tb: spiflash_tb.vvp firmware.hex
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spiflash_tb.vvp: spiflash.v spiflash_tb.v
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iverilog -s testbench -o $@ $^
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# ---- ASIC Synthesis Tests ----
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cmos.log: spimemio.v simpleuart.v picosoc.v ../picorv32.v
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yosys -l cmos.log -p 'synth -top picosoc; abc -g cmos2; opt -fast; stat' $^
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# ---- Clean ----
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clean:
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rm -f testbench.vvp testbench.vcd spiflash_tb.vvp spiflash_tb.vcd
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rm -f firmware.elf firmware.hex firmware.bin
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rm -f firmware.elf firmware.hex firmware.bin cmos.log
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rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
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rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp
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@ -17,6 +17,12 @@
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*
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*/
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`ifdef PICORV32_V
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`error "picosoc.v must be read before picorv32.v!"
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`endif
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`define PICORV32_REGS picosoc_regs
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module picosoc (
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input clk,
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input resetn,
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@ -82,7 +88,7 @@ module picosoc (
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wire [31:0] spimem_rdata;
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reg ram_ready;
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reg [31:0] ram_rdata;
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wire [31:0] ram_rdata;
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assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
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assign iomem_wstrb = mem_wstrb;
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@ -178,17 +184,56 @@ module picosoc (
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.reg_dat_wait(simpleuart_reg_dat_wait)
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);
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reg [31:0] memory [0:MEM_WORDS-1];
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always @(posedge clk)
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ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
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picosoc_mem #(.WORDS(MEM_WORDS)) memory (
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.clk(clk),
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.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
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.addr(mem_addr[23:2]),
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.wdata(mem_wdata),
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.rdata(ram_rdata)
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);
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endmodule
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// Implementation note:
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// Replace the following two modules with wrappers for your SRAM cells.
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module picosoc_regs (
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input clk, wen,
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input [5:0] waddr,
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input [5:0] raddr1,
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input [5:0] raddr2,
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input [31:0] wdata,
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output [31:0] rdata1,
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output [31:0] rdata2
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);
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reg [31:0] regs [0:31];
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always @(posedge clk)
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if (wen) regs[waddr[4:0]] <= wdata;
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assign rdata1 = regs[raddr1[4:0]];
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assign rdata2 = regs[raddr2[4:0]];
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endmodule
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module picosoc_mem #(
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parameter integer WORDS = 256
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) (
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input clk,
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input [3:0] wen,
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input [21:0] addr,
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input [31:0] wdata,
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output reg [31:0] rdata
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);
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reg [31:0] mem [0:WORDS-1];
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always @(posedge clk) begin
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ram_ready <= 0;
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if (mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) begin
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ram_ready <= 1;
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ram_rdata <= memory[mem_addr >> 2];
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end
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rdata <= mem[addr];
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if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
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if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
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if (wen[2]) mem[addr][23:16] <= wdata[23:16];
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if (wen[3]) mem[addr][31:24] <= wdata[31:24];
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end
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endmodule
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