colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

scripts/icestorm: dedupe calls to yosys-config 

Signed-off-by: Austin Seipp <aseipp@pobox.com>
This commit is contained in:
Austin Seipp 2019-01-11 16:49:18 -06:00
parent 770b5bd4c6
commit af3b1bb75d
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
scripts/icestorm/Makefile
View File

@ -1,5 +1,7 @@
TOOLCHAIN_PREFIX = riscv32-unknown-elf- TOOLCHAIN_PREFIX = riscv32-unknown-elf-
ICE40_SIM_CELLS=$(shell yosys-config --datdir/ice40/cells_sim.v)
# set to 4 for simulation # set to 4 for simulation
FIRMWARE_COUNTER_BITS=18 FIRMWARE_COUNTER_BITS=18
@ -52,7 +54,7 @@ example_sim_vcd: example_tb.vvp
## post-synth simulation ## post-synth simulation
synth_tb.vvp: example_tb.v synth.json synth_tb.vvp: example_tb.v synth.json
iverilog -o $@ -s testbench synth.v example_tb.v `yosys-config --datdir/ice40/cells_sim.v` iverilog -o $@ -s testbench synth.v example_tb.v $(ICE40_SIM_CELLS)
chmod -x $@ chmod -x $@
synth_sim: synth_tb.vvp synth_sim: synth_tb.vvp
@ -68,7 +70,7 @@ route.v: example.asc example.pcf
icebox_vlog -L -n top -sp example.pcf $< > $@ icebox_vlog -L -n top -sp example.pcf $< > $@
route_tb.vvp: route.v example_tb.v route_tb.vvp: route.v example_tb.v
iverilog -o $@ -s testbench $^ `yosys-config --datdir/ice40/cells_sim.v` iverilog -o $@ -s testbench $^ $(ICE40_SIM_CELLS)
chmod -x $@ chmod -x $@
route_sim: route_tb.vvp route_sim: route_tb.vvp