From af85947a58c92b3b9756f1e2922031135c1e4418 Mon Sep 17 00:00:00 2001 From: "colin.liang" Date: Thu, 12 Jan 2023 16:09:10 +0800 Subject: [PATCH] Remote ENABLE_REGS_DUALPORT and init reg zero. --- picorv32.v | 134 ++++++++++++++++++++--------------------------------- 1 file changed, 51 insertions(+), 83 deletions(-) diff --git a/picorv32.v b/picorv32.v index 58c3648..50fdd78 100644 --- a/picorv32.v +++ b/picorv32.v @@ -52,7 +52,6 @@ module picorv32 #( parameter [ 0:0] ENABLE_REGS_16_31 = 1, - parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, parameter [ 0:0] LATCHED_MEM_RDATA = 0, parameter [ 0:0] TWO_STAGE_SHIFT = 1, parameter [ 0:0] BARREL_SHIFTER = 0, @@ -66,7 +65,6 @@ module picorv32 #( parameter [ 0:0] ENABLE_IRQ_QREGS = 1, parameter [ 0:0] ENABLE_IRQ_TIMER = 1, parameter [ 0:0] ENABLE_TRACE = 0, - parameter [ 0:0] REGS_INIT_ZERO = 0, parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, @@ -153,14 +151,6 @@ module picorv32 #( `ifndef PICORV32_REGS reg [31:0] cpuregs [0:regfile_size-1]; - - integer i; - initial begin - if (REGS_INIT_ZERO) begin - for (i = 0; i < regfile_size; i = i+1) - cpuregs[i] = 0; - end - end `endif task empty_statement; @@ -964,31 +954,22 @@ module picorv32 #( always @* begin decoded_rs = 'bx; - if (ENABLE_REGS_DUALPORT) begin `ifndef RISCV_FORMAL_BLACKBOX_REGS - cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; - cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; + cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; `else - cpuregs_rs1 = decoded_rs1 ? $anyseq : 0; - cpuregs_rs2 = decoded_rs2 ? $anyseq : 0; + cpuregs_rs1 = decoded_rs1 ? $anyseq : 0; + cpuregs_rs2 = decoded_rs2 ? $anyseq : 0; `endif - end else begin - decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; -`ifndef RISCV_FORMAL_BLACKBOX_REGS - cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0; -`else - cpuregs_rs1 = decoded_rs ? $anyseq : 0; -`endif - cpuregs_rs2 = cpuregs_rs1; - end + end `else wire[31:0] cpuregs_rdata1; wire[31:0] cpuregs_rdata2; wire [5:0] cpuregs_waddr = latched_rd; - wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs; - wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0; + wire [5:0] cpuregs_raddr1 = decoded_rs1; + wire [5:0] cpuregs_raddr2 = decoded_rs2; `PICORV32_REGS cpuregs ( .clk(clk), @@ -1003,14 +984,8 @@ module picorv32 #( always @* begin decoded_rs = 'bx; - if (ENABLE_REGS_DUALPORT) begin - cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; - cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0; - end else begin - decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; - cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0; - cpuregs_rs2 = cpuregs_rs1; - end + cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0; end `endif @@ -1193,31 +1168,27 @@ module picorv32 #( reg_op1 <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1; dbg_rs1val_valid <= 1; - if (ENABLE_REGS_DUALPORT) begin - pcpi_valid <= 1; - `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) - reg_sh <= cpuregs_rs2; - reg_op2 <= cpuregs_rs2; - dbg_rs2val <= cpuregs_rs2; - dbg_rs2val_valid <= 1; - if (pcpi_int_ready) begin - mem_do_rinst <= 1; - pcpi_valid <= 0; - reg_out <= pcpi_int_rd; - latched_store <= pcpi_int_wr; + pcpi_valid <= 1; + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (pcpi_timeout || instr_ecall_ebreak) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; cpu_state <= cpu_state_fetch; end else - if (pcpi_timeout || instr_ecall_ebreak) begin - pcpi_valid <= 0; - `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin - next_irq_pending[irq_ebreak] = 1; - cpu_state <= cpu_state_fetch; - end else - cpu_state <= cpu_state_trap; - end - end else begin - cpu_state <= cpu_state_ld_rs2; + cpu_state <= cpu_state_trap; end end else begin `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) @@ -1331,32 +1302,29 @@ module picorv32 #( reg_op1 <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1; dbg_rs1val_valid <= 1; - if (ENABLE_REGS_DUALPORT) begin - `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) - reg_sh <= cpuregs_rs2; - reg_op2 <= cpuregs_rs2; - dbg_rs2val <= cpuregs_rs2; - dbg_rs2val_valid <= 1; - (* parallel_case *) - case (1'b1) - is_sb_sh_sw: begin - cpu_state <= cpu_state_stmem; - mem_do_rinst <= 1; - end - is_sll_srl_sra && !BARREL_SHIFTER: begin - cpu_state <= cpu_state_shift; - end - default: begin - if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin - alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); - alu_wait <= 1; - end else - mem_do_rinst <= mem_do_prefetch; - cpu_state <= cpu_state_exec; - end - endcase - end else - cpu_state <= cpu_state_ld_rs2; + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + (* parallel_case *) + case (1'b1) + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase end endcase end