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remove irq in testbench.

This commit is contained in:
colin.liang 2023-01-17 13:01:41 +08:00
parent dcab0c3178
commit b03844d9ac
1 changed files with 0 additions and 12 deletions
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12
testbench_wb.v
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@ -9,18 +9,11 @@ module picorv32_wrapper #(
input [1024:0] hex_file input [1024:0] hex_file
); );
wire exit; wire exit;
reg [31:0] irq = 0;
wire mem_instr; wire mem_instr;
reg [15:0] count_cycle = 0; reg [15:0] count_cycle = 0;
always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0; always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire [31:0] wb_m2s_adr; wire [31:0] wb_m2s_adr;
wire [31:0] wb_m2s_dat; wire [31:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel; wire [3:0] wb_m2s_sel;
@ -33,7 +26,6 @@ module picorv32_wrapper #(
picorv32_wb #() uut ( picorv32_wb #() uut (
.trap(trap), .trap(trap),
.exit(exit), .exit(exit),
.irq(irq),
.mem_instr(mem_instr), .mem_instr(mem_instr),
.wb_clk_i(wb_clk), .wb_clk_i(wb_clk),
@ -71,10 +63,6 @@ module picorv32_wb #(
input wb_rst_i, input wb_rst_i,
input wb_clk_i, input wb_clk_i,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
output mem_instr output mem_instr
); );
wire mem_valid; wire mem_valid;