Fixed PCPI instr prefetching
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@ -195,7 +195,7 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT.
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| shift operations | 4-14 | 4-15 |
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| shift operations | 4-14 | 4-15 |
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When `ENABLE_MUL` is activated, then a `MUL` instruction will execute
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When `ENABLE_MUL` is activated, then a `MUL` instruction will execute
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in 42 cycles and a `MULH[SU|U]` instruction will execute in 74 cycles.
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in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles.
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Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz)
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Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz)
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@ -405,12 +405,13 @@ enabled PCPI, IRQ and MUL features.
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| PicoRV32 "regular" | 996 | 48 |
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| PicoRV32 "regular" | 996 | 48 |
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| PicoRV32 "large" | 1814 | 88 |
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| PicoRV32 "large" | 1814 | 88 |
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*Note: Most of the size reduction in the "small" core comes from eliminating
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the counter instructions, not from reducing the size of the register file.*
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Todos:
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Todos:
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------
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------
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- Optional FENCE support
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- Optional write-through cache
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- Optional support for compressed ISA
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- Optional support for compressed ISA
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- Improved documentation and examples
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- Improved documentation and examples
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@ -164,8 +164,7 @@ module picorv32 #(
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reg mem_do_wdata;
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reg mem_do_wdata;
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wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
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wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
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wire mem_done = (mem_ready && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst);
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wire mem_done = mem_ready && ((mem_state[0] && (mem_do_rinst || mem_do_rdata)) || mem_state == 2);
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assign mem_la_write = resetn && !mem_state && mem_do_wdata;
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assign mem_la_write = resetn && !mem_state && mem_do_wdata;
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assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);
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assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);
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