diff --git a/picorv32.v b/picorv32.v
index d544995..99ac859 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -45,7 +45,6 @@
 module picorv32 #(
     parameter [0:0] TWO_STAGE_SHIFT = 1,
     parameter [0:0] BARREL_SHIFTER = 0,
-    parameter [0:0] TWO_CYCLE_COMPARE = 0,
     parameter [0:0] ENABLE_TRACE = 0,
     parameter [31:0] MASKED_IRQ = 32'h0000_0000,
     parameter [31:0] LATCHED_IRQ = 32'hffff_ffff,
@@ -810,7 +809,6 @@ module picorv32 #(
 
   reg [31:0] alu_out, alu_out_q;
   reg alu_out_0, alu_out_0_q;
-  reg alu_wait, alu_wait_2;  // AAAA
 
   reg [31:0] alu_add_sub;
   reg [31:0] alu_shl, alu_shr;
@@ -833,10 +831,8 @@ module picorv32 #(
       instr_bne: alu_out_0 = !alu_eq;
       instr_bge: alu_out_0 = !alu_lts;
       instr_bgeu: alu_out_0 = !alu_ltu;
-      is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
-      alu_out_0 = alu_lts;
-      is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
-      alu_out_0 = alu_ltu;
+      is_slti_blt_slt: alu_out_0 = alu_lts;
+      is_sltiu_bltu_sltu: alu_out_0 = alu_ltu;
     endcase
 
     alu_out = 'bx;
@@ -922,9 +918,6 @@ module picorv32 #(
     alu_out_0_q <= alu_out_0;
     alu_out_q <= alu_out;
 
-    alu_wait <= 0;
-    alu_wait_2 <= 0;
-
     if (launch_next_insn) begin
       dbg_rs1val <= 'bx;
       dbg_rs2val <= 'bx;
@@ -1206,10 +1199,7 @@ module picorv32 #(
                   cpu_state <= cpu_state_shift;
                 end
                 default: begin
-                  if (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu) begin
-                    alu_wait_2 <= 0; // AAAA
-                    alu_wait <= 1;
-                  end else mem_do_rinst <= mem_do_prefetch;
+                  mem_do_rinst <= mem_do_prefetch;
                   cpu_state <= cpu_state_exec;
                 end
               endcase
@@ -1251,10 +1241,7 @@ module picorv32 #(
               cpu_state <= cpu_state_shift;
             end
             default: begin
-              if ((TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
-                alu_wait_2 <= 0; // AAAA
-                alu_wait   <= 1;
-              end else mem_do_rinst <= mem_do_prefetch;
+              mem_do_rinst <= mem_do_prefetch;
               cpu_state <= cpu_state_exec;
             end
           endcase
@@ -1262,15 +1249,12 @@ module picorv32 #(
 
         cpu_state_exec: begin
           reg_out <= reg_pc + decoded_imm;
-          if (TWO_CYCLE_COMPARE && (alu_wait || alu_wait_2)) begin
-            mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
-            alu_wait <= alu_wait_2;
-          end else if (is_beq_bne_blt_bge_bltu_bgeu) begin
+          if (is_beq_bne_blt_bge_bltu_bgeu) begin
             latched_rd <= 0;
-            latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
-            latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+            latched_store <= alu_out_0;
+            latched_branch <= alu_out_0;
             if (mem_done) cpu_state <= cpu_state_fetch;
-            if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
+            if (alu_out_0) begin
               decoder_trigger <= 0;
               set_mem_do_rinst = 1;
             end