Remove counter parameter. Default enable.
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f714dd5da4
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26
picorv32.v
26
picorv32.v
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@ -999,11 +999,11 @@ module picorv32 #(
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instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
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instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
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(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
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(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010));
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instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
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(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
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instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
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instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
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(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010));
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instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010);
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instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010);
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instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
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(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
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@ -1345,15 +1345,7 @@ module picorv32 #(
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pcpi_timeout_counter <= ~0;
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pcpi_timeout <= !pcpi_timeout_counter;
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end
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if (ENABLE_COUNTERS) begin
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count_cycle <= resetn ? count_cycle + 1 : 0;
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if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
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end else begin
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count_cycle <= 'bx;
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count_instr <= 'bx;
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end
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next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
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if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
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@ -1374,7 +1366,6 @@ module picorv32 #(
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if (!resetn) begin
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reg_pc <= PROGADDR_RESET;
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reg_next_pc <= PROGADDR_RESET;
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if (ENABLE_COUNTERS)
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count_instr <= 0;
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latched_store <= 0;
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latched_stalu <= 0;
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@ -1477,10 +1468,7 @@ module picorv32 #(
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reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
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if (ENABLE_TRACE)
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latched_trace <= 1;
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if (ENABLE_COUNTERS) begin
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count_instr <= count_instr + 1;
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if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
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end
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if (instr_jal) begin
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mem_do_rinst <= 1;
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reg_next_pc <= current_pc + decoded_imm_j;
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@ -1540,16 +1528,16 @@ module picorv32 #(
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cpu_state <= cpu_state_trap;
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end
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end
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ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
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is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
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(* parallel_case, full_case *)
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case (1'b1)
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instr_rdcycle:
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reg_out <= count_cycle[31:0];
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instr_rdcycleh && ENABLE_COUNTERS64:
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instr_rdcycleh:
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reg_out <= count_cycle[63:32];
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instr_rdinstr:
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reg_out <= count_instr[31:0];
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instr_rdinstrh && ENABLE_COUNTERS64:
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instr_rdinstrh:
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reg_out <= count_instr[63:32];
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endcase
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latched_store <= 1;
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