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remove TWO_CYCLE_ALU.

This commit is contained in:
colin.liang 2023-01-12 17:31:14 +08:00
parent 4beed17d0a
commit bb0bf253eb
1 changed files with 16 additions and 34 deletions
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picorv32.v
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@ -46,7 +46,6 @@ module picorv32 #(
parameter [0:0] TWO_STAGE_SHIFT = 1, parameter [0:0] TWO_STAGE_SHIFT = 1,
parameter [0:0] BARREL_SHIFTER = 0, parameter [0:0] BARREL_SHIFTER = 0,
parameter [0:0] TWO_CYCLE_COMPARE = 0, parameter [0:0] TWO_CYCLE_COMPARE = 0,
parameter [0:0] TWO_CYCLE_ALU = 0,
parameter [0:0] ENABLE_TRACE = 0, parameter [0:0] ENABLE_TRACE = 0,
parameter [31:0] MASKED_IRQ = 32'h0000_0000, parameter [31:0] MASKED_IRQ = 32'h0000_0000,
parameter [31:0] LATCHED_IRQ = 32'hffff_ffff, parameter [31:0] LATCHED_IRQ = 32'hffff_ffff,
@ -811,35 +810,20 @@ module picorv32 #(
reg [31:0] alu_out, alu_out_q; reg [31:0] alu_out, alu_out_q;
reg alu_out_0, alu_out_0_q; reg alu_out_0, alu_out_0_q;
reg alu_wait, alu_wait_2; reg alu_wait, alu_wait_2; // AAAA
reg [31:0] alu_add_sub; reg [31:0] alu_add_sub;
reg [31:0] alu_shl, alu_shr; reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts; reg alu_eq, alu_ltu, alu_lts;
generate always @* begin
if (TWO_CYCLE_ALU) begin alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
always @(posedge clk) begin alu_eq = reg_op1 == reg_op2;
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_eq <= reg_op1 == reg_op2; alu_ltu = reg_op1 < reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2); alu_shl = reg_op1 << reg_op2[4:0];
alu_ltu <= reg_op1 < reg_op2; alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
alu_shl <= reg_op1 << reg_op2[4:0]; end
alu_shr <= $signed(
{instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}
) >>> reg_op2[4:0];
end
end else begin
always @* begin
alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq = reg_op1 == reg_op2;
alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_ltu = reg_op1 < reg_op2;
alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end
endgenerate
always @* begin always @* begin
alu_out_0 = 'bx; alu_out_0 = 'bx;
@ -1128,8 +1112,7 @@ module picorv32 #(
is_lui_auipc_jal: begin is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc; reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm; reg_op2 <= decoded_imm;
if (TWO_CYCLE_ALU) alu_wait <= 1; mem_do_rinst <= mem_do_prefetch;
else mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
instr_getq: begin instr_getq: begin
@ -1200,8 +1183,7 @@ module picorv32 #(
dbg_rs1val <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1; dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm; reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
if (TWO_CYCLE_ALU) alu_wait <= 1; mem_do_rinst <= mem_do_prefetch;
else mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
end end
default: begin default: begin
@ -1224,8 +1206,8 @@ module picorv32 #(
cpu_state <= cpu_state_shift; cpu_state <= cpu_state_shift;
end end
default: begin default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin if (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); alu_wait_2 <= 0; // AAAA
alu_wait <= 1; alu_wait <= 1;
end else mem_do_rinst <= mem_do_prefetch; end else mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
@ -1269,8 +1251,8 @@ module picorv32 #(
cpu_state <= cpu_state_shift; cpu_state <= cpu_state_shift;
end end
default: begin default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin if ((TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); alu_wait_2 <= 0; // AAAA
alu_wait <= 1; alu_wait <= 1;
end else mem_do_rinst <= mem_do_prefetch; end else mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec; cpu_state <= cpu_state_exec;
@ -1280,7 +1262,7 @@ module picorv32 #(
cpu_state_exec: begin cpu_state_exec: begin
reg_out <= reg_pc + decoded_imm; reg_out <= reg_pc + decoded_imm;
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin if (TWO_CYCLE_COMPARE && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2; mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2; alu_wait <= alu_wait_2;
end else if (is_beq_bne_blt_bge_bltu_bgeu) begin end else if (is_beq_bne_blt_bge_bltu_bgeu) begin