Refactoring of TWO_CYCLE_ALU
This commit is contained in:
Clifford Wolf
parent
51be282633
commit
bf7f984d42
248
picorv32.v
248
picorv32.v
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@ -18,6 +18,7 @@
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*/
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`timescale 1 ns / 1 ps
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// `default_nettype none
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// `define DEBUG
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`ifdef DEBUG
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@ -282,7 +283,7 @@ module picorv32 #(
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reg is_jalr_addi_slti_sltiu_xori_ori_andi;
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reg is_sb_sh_sw;
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reg is_sll_srl_sra;
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reg is_lui_auipc_jal_jalr_addi_add;
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reg is_lui_auipc_jal_jalr_addi_add_sub;
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reg is_slti_blt_slt;
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reg is_sltiu_bltu_sltu;
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reg is_beq_bne_blt_bge_bltu_bgeu;
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@ -302,72 +303,72 @@ module picorv32 #(
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wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
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assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
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reg [63:0] new_instruction;
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reg [63:0] instruction;
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reg [63:0] new_ascii_instr;
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reg [63:0] ascii_instr;
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always @* begin
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new_instruction = "";
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if (instr_lui) new_instruction = "lui";
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if (instr_auipc) new_instruction = "auipc";
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if (instr_jal) new_instruction = "jal";
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if (instr_jalr) new_instruction = "jalr";
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new_ascii_instr = "";
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if (instr_lui) new_ascii_instr = "lui";
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if (instr_auipc) new_ascii_instr = "auipc";
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if (instr_jal) new_ascii_instr = "jal";
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if (instr_jalr) new_ascii_instr = "jalr";
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if (instr_beq) new_instruction = "beq";
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if (instr_bne) new_instruction = "bne";
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if (instr_blt) new_instruction = "blt";
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if (instr_bge) new_instruction = "bge";
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if (instr_bltu) new_instruction = "bltu";
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if (instr_bgeu) new_instruction = "bgeu";
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if (instr_beq) new_ascii_instr = "beq";
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if (instr_bne) new_ascii_instr = "bne";
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if (instr_blt) new_ascii_instr = "blt";
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if (instr_bge) new_ascii_instr = "bge";
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if (instr_bltu) new_ascii_instr = "bltu";
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if (instr_bgeu) new_ascii_instr = "bgeu";
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if (instr_lb) new_instruction = "lb";
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if (instr_lh) new_instruction = "lh";
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if (instr_lw) new_instruction = "lw";
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if (instr_lbu) new_instruction = "lbu";
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if (instr_lhu) new_instruction = "lhu";
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if (instr_sb) new_instruction = "sb";
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if (instr_sh) new_instruction = "sh";
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if (instr_sw) new_instruction = "sw";
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if (instr_lb) new_ascii_instr = "lb";
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if (instr_lh) new_ascii_instr = "lh";
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if (instr_lw) new_ascii_instr = "lw";
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if (instr_lbu) new_ascii_instr = "lbu";
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if (instr_lhu) new_ascii_instr = "lhu";
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if (instr_sb) new_ascii_instr = "sb";
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if (instr_sh) new_ascii_instr = "sh";
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if (instr_sw) new_ascii_instr = "sw";
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if (instr_addi) new_instruction = "addi";
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if (instr_slti) new_instruction = "slti";
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if (instr_sltiu) new_instruction = "sltiu";
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if (instr_xori) new_instruction = "xori";
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if (instr_ori) new_instruction = "ori";
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if (instr_andi) new_instruction = "andi";
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if (instr_slli) new_instruction = "slli";
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if (instr_srli) new_instruction = "srli";
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if (instr_srai) new_instruction = "srai";
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if (instr_addi) new_ascii_instr = "addi";
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if (instr_slti) new_ascii_instr = "slti";
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if (instr_sltiu) new_ascii_instr = "sltiu";
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if (instr_xori) new_ascii_instr = "xori";
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if (instr_ori) new_ascii_instr = "ori";
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if (instr_andi) new_ascii_instr = "andi";
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if (instr_slli) new_ascii_instr = "slli";
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if (instr_srli) new_ascii_instr = "srli";
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if (instr_srai) new_ascii_instr = "srai";
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if (instr_add) new_instruction = "add";
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if (instr_sub) new_instruction = "sub";
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if (instr_sll) new_instruction = "sll";
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if (instr_slt) new_instruction = "slt";
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if (instr_sltu) new_instruction = "sltu";
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if (instr_xor) new_instruction = "xor";
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if (instr_srl) new_instruction = "srl";
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if (instr_sra) new_instruction = "sra";
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if (instr_or) new_instruction = "or";
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if (instr_and) new_instruction = "and";
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if (instr_add) new_ascii_instr = "add";
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if (instr_sub) new_ascii_instr = "sub";
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if (instr_sll) new_ascii_instr = "sll";
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if (instr_slt) new_ascii_instr = "slt";
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if (instr_sltu) new_ascii_instr = "sltu";
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if (instr_xor) new_ascii_instr = "xor";
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if (instr_srl) new_ascii_instr = "srl";
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if (instr_sra) new_ascii_instr = "sra";
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if (instr_or) new_ascii_instr = "or";
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if (instr_and) new_ascii_instr = "and";
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if (instr_rdcycle) new_instruction = "rdcycle";
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if (instr_rdcycleh) new_instruction = "rdcycleh";
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if (instr_rdinstr) new_instruction = "rdinstr";
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if (instr_rdinstrh) new_instruction = "rdinstrh";
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if (instr_rdcycle) new_ascii_instr = "rdcycle";
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if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
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if (instr_rdinstr) new_ascii_instr = "rdinstr";
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if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
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if (instr_getq) new_instruction = "getq";
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if (instr_setq) new_instruction = "setq";
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if (instr_retirq) new_instruction = "retirq";
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if (instr_maskirq) new_instruction = "maskirq";
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if (instr_waitirq) new_instruction = "waitirq";
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if (instr_timer) new_instruction = "timer";
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if (instr_getq) new_ascii_instr = "getq";
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if (instr_setq) new_ascii_instr = "setq";
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if (instr_retirq) new_ascii_instr = "retirq";
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if (instr_maskirq) new_ascii_instr = "maskirq";
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if (instr_waitirq) new_ascii_instr = "waitirq";
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if (instr_timer) new_ascii_instr = "timer";
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if (decoder_trigger_q)
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instruction = new_instruction;
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ascii_instr = new_ascii_instr;
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end
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always @(posedge clk) begin
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is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
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is_lui_auipc_jal_jalr_addi_add <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add};
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is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
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is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
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is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
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is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
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@ -510,6 +511,20 @@ module picorv32 #(
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reg [7:0] cpu_state;
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reg [1:0] irq_state;
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reg [127:0] ascii_state;
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always @* begin
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ascii_state = "";
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if (cpu_state == cpu_state_trap) ascii_state = "trap";
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if (cpu_state == cpu_state_fetch) ascii_state = "fetch";
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if (cpu_state == cpu_state_ld_rs1) ascii_state = "ld_rs1";
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if (cpu_state == cpu_state_ld_rs2) ascii_state = "ld_rs2";
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if (cpu_state == cpu_state_exec) ascii_state = "exec";
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if (cpu_state == cpu_state_shift) ascii_state = "shift";
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if (cpu_state == cpu_state_stmem) ascii_state = "stmem";
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if (cpu_state == cpu_state_ldmem) ascii_state = "ldmem";
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end
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reg set_mem_do_rinst;
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reg set_mem_do_rdata;
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reg set_mem_do_wdata;
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@ -535,100 +550,59 @@ module picorv32 #(
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reg alu_out_0, alu_out_0_q;
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reg alu_wait, alu_wait_2;
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always @* begin
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end
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generate if (TWO_CYCLE_ALU) begin:two_cycle_alu
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reg [31:0] alu_add_sub;
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reg [31:0] alu_xor_or_and;
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reg alu_eq, alu_ltu, alu_lts;
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reg [31:0] alu_add_sub;
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reg alu_eq, alu_ltu, alu_lts;
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generate if (TWO_CYCLE_ALU) begin
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always @(posedge clk) begin
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alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
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alu_xor_or_and = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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instr_xori || instr_xor:
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alu_xor_or_and = reg_op1 ^ reg_op2;
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instr_ori || instr_or:
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alu_xor_or_and = reg_op1 | reg_op2;
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instr_andi || instr_and:
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alu_xor_or_and = reg_op1 & reg_op2;
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endcase
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alu_eq <= reg_op1 == reg_op2;
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alu_lts <= $signed(reg_op1) < $signed(reg_op2);
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alu_ltu <= reg_op1 < reg_op2;
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end
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end else begin
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always @* begin
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alu_out_0 = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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instr_beq:
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alu_out_0 = alu_eq;
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instr_bne:
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alu_out_0 = !alu_eq;
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instr_bge:
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alu_out_0 = !alu_lts;
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instr_bgeu:
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alu_out_0 = !alu_ltu;
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is_slti_blt_slt:
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alu_out_0 = alu_lts;
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is_sltiu_bltu_sltu:
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alu_out_0 = alu_ltu;
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endcase
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alu_out = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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is_lui_auipc_jal_jalr_addi_add || instr_sub:
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alu_out = alu_add_sub;
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is_compare:
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alu_out = alu_out_0;
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|{instr_xori, instr_xor, instr_ori, instr_or, instr_andi, instr_and}:
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alu_out = alu_xor_or_and;
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endcase
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end
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end else begin:one_cycle_alu
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always @* begin
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alu_out_0 = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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instr_beq:
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alu_out_0 = reg_op1 == reg_op2;
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instr_bne:
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alu_out_0 = reg_op1 != reg_op2;
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instr_bge:
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alu_out_0 = $signed(reg_op1) >= $signed(reg_op2);
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instr_bgeu:
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alu_out_0 = reg_op1 >= reg_op2;
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is_slti_blt_slt:
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alu_out_0 = $signed(reg_op1) < $signed(reg_op2);
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is_sltiu_bltu_sltu:
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alu_out_0 = reg_op1 < reg_op2;
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endcase
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alu_out = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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is_lui_auipc_jal_jalr_addi_add:
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alu_out = reg_op1 + reg_op2;
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instr_sub:
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alu_out = reg_op1 - reg_op2;
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is_compare:
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alu_out = alu_out_0;
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instr_xori || instr_xor:
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alu_out = reg_op1 ^ reg_op2;
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instr_ori || instr_or:
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alu_out = reg_op1 | reg_op2;
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instr_andi || instr_and:
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alu_out = reg_op1 & reg_op2;
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endcase
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alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
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alu_eq = reg_op1 == reg_op2;
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alu_lts = $signed(reg_op1) < $signed(reg_op2);
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alu_ltu = reg_op1 < reg_op2;
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end
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end endgenerate
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always @* begin
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alu_out_0 = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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instr_beq:
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alu_out_0 = alu_eq;
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instr_bne:
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alu_out_0 = !alu_eq;
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instr_bge:
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alu_out_0 = !alu_lts;
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instr_bgeu:
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alu_out_0 = !alu_ltu;
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is_slti_blt_slt:
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alu_out_0 = alu_lts;
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is_sltiu_bltu_sltu:
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alu_out_0 = alu_ltu;
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endcase
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alu_out = 'bx;
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(* parallel_case, full_case *)
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case (1'b1)
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is_lui_auipc_jal_jalr_addi_add_sub:
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alu_out = alu_add_sub;
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is_compare:
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alu_out = alu_out_0;
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instr_xori || instr_xor:
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alu_out = reg_op1 ^ reg_op2;
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instr_ori || instr_or:
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alu_out = reg_op1 | reg_op2;
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instr_andi || instr_and:
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alu_out = reg_op1 & reg_op2;
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endcase
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end
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always @(posedge clk) begin
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trap <= 0;
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reg_sh <= 'bx;
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@ -778,7 +752,7 @@ module picorv32 #(
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cpu_state_ld_rs1: begin
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reg_op1 <= 'bx;
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reg_op2 <= 'bx;
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`debug($display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");)
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`debug($display("DECODE: 0x%08x %-0s", reg_pc, ascii_instr ? ascii_instr : "UNKNOWN");)
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(* parallel_case *)
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case (1'b1)
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