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Fix decoding of illegal/reserved opcodes as other valid opcodes

This commit is contained in:
Clifford Wolf 2017-05-07 21:13:46 +02:00
parent a13512c86a
commit bf9687028d
1 changed files with 29 additions and 21 deletions
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14
picorv32.v
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@ -835,7 +835,7 @@ module picorv32 #(
instr_lui <= mem_rdata_latched[6:0] == 7'b0110111; instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111; instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
instr_jal <= mem_rdata_latched[6:0] == 7'b1101111; instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111; instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ; instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ; instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
@ -890,10 +890,12 @@ module picorv32 #(
2'b01: begin // Quadrant 1 2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13]) case (mem_rdata_latched[15:13])
3'b000: begin // C.NOP / C.ADDI 3'b000: begin // C.NOP / C.ADDI
if (!mem_rdata_latched[12:2] || mem_rdata_latched[11:7]) begin
is_alu_reg_imm <= 1; is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7]; decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7]; decoded_rs1 <= mem_rdata_latched[11:7];
end end
end
3'b001: begin // C.JAL 3'b001: begin // C.JAL
instr_jal <= 1; instr_jal <= 1;
decoded_rd <= 1; decoded_rd <= 1;
@ -904,6 +906,7 @@ module picorv32 #(
decoded_rs1 <= 0; decoded_rs1 <= 0;
end end
3'b 011: begin 3'b 011: begin
if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
is_alu_reg_imm <= 1; is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7]; decoded_rd <= mem_rdata_latched[11:7];
@ -914,8 +917,9 @@ module picorv32 #(
decoded_rs1 <= 0; decoded_rs1 <= 0;
end end
end end
end
3'b100: begin 3'b100: begin
if (mem_rdata_latched[11] == 1'b0) begin // C.SRLI, C.SRAI if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
is_alu_reg_imm <= 1; is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7]; decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7]; decoded_rs1 <= 8 + mem_rdata_latched[9:7];
@ -951,18 +955,22 @@ module picorv32 #(
2'b10: begin // Quadrant 2 2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13]) case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI 3'b000: begin // C.SLLI
if (!mem_rdata_latched[12]) begin
is_alu_reg_imm <= 1; is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7]; decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7]; decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end end
end
3'b010: begin // C.LWSP 3'b010: begin // C.LWSP
if (mem_rdata_latched[11:7]) begin
is_lb_lh_lw_lbu_lhu <= 1; is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7]; decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2; decoded_rs1 <= 2;
end end
end
3'b100: begin 3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
instr_jalr <= 1; instr_jalr <= 1;
decoded_rd <= 0; decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7]; decoded_rs1 <= mem_rdata_latched[11:7];