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Towards compressed ISA support

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Clifford Wolf 2015-11-15 16:04:04 +01:00
parent bf4b0f3a63
commit bfd2a4e0fa
1 changed files with 50 additions and 0 deletions
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picorv32.v
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@ -256,10 +256,32 @@ module picorv32 #(
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end end
end end
3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:15], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
3'b 111: begin // C.BNEZ
mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:15], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
endcase endcase
end end
2'b10: begin // Quadrant 2 2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13]) case (mem_rdata_latched[15:13])
3'b010: begin // C.LWSP
mem_rdata_q[31:20] <= {mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end
3'b110: begin // C.SWSP 3'b110: begin // C.SWSP
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
mem_rdata_q[14:12] <= 3'b 010; mem_rdata_q[14:12] <= 3'b 010;
@ -521,10 +543,38 @@ module picorv32 #(
3'b101: begin // C.J 3'b101: begin // C.J
instr_jal <= 1; instr_jal <= 1;
end end
3'b110: begin // C.BEQZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
3'b111: begin // C.BNEZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
endcase endcase
end end
2'b10: begin // Quadrant 2 2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13]) case (mem_rdata_latched[15:13])
3'b010: begin // C.LWSP
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
instr_jalr <= 1;
decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
decoded_rs2 <= mem_rdata_latched[6:2];
end
end
3'b110: begin // C.SWSP 3'b110: begin // C.SWSP
is_sb_sh_sw <= 1; is_sb_sh_sw <= 1;
decoded_rs1 <= 2; decoded_rs1 <= 2;