Add PicoSoC spimem Dual I/O support
This commit is contained in:
Clifford Wolf
parent
c00811e8e4
commit
c06ba38113
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@ -55,8 +55,8 @@ GPIO pins mapped to the 32 bit word at address 0x03000000.
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| 30:23 | Reserved (read 0) |
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| 22 | DDR Enable bit (reset=0) |
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| 21 | QSPI Enable bit (reset=0) |
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| 20 | XIP Enable bit (reset=0) |
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| 19:16 | Number of QSPI dummy cycles (reset=0) |
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| 20 | CRM Enable bit (reset=0) |
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| 19:16 | Read latency (dummy) cycles (reset=0) |
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| 15:12 | Reserved (read 0) |
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| 11:8 | IO Output enable bits in bit bang mode |
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| 7:6 | Reserved (read 0) |
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@ -64,13 +64,15 @@ GPIO pins mapped to the 32 bit word at address 0x03000000.
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| 4 | Serial clock line in bit bang mode |
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| 3:0 | IO data bits in bit bang mode |
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The following settings for XIP/DDR/QSPI modes are valid:
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The following settings for CRM/DDR/QSPI modes are valid:
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| XIP | DDR | QSPI | Read Command Byte | Mode Byte |
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| :-: | :-: | :--: | :-------------------- | :-------: |
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| CRM | QSPI | DDR | Read Command Byte | Mode Byte |
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| :-: | :--: | :-: | :-------------------- | :-------: |
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| 0 | 0 | 0 | 03h Read | N/A |
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| 0 | 0 | 1 | EBh Quad I/O Read | FFh |
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| 1 | 0 | 1 | EBh Quad I/O Read | A5h / FFh |
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| 0 | 0 | 1 | BBh Dual I/O Read | FFh |
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| 1 | 0 | 1 | BBh Dual I/O Read | A5h |
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| 0 | 1 | 0 | EBh Quad I/O Read | FFh |
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| 1 | 1 | 0 | EBh Quad I/O Read | A5h |
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| 0 | 1 | 1 | EDh DDR Quad I/O Read | FFh |
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| 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h / FFh |
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| 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h |
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@ -26,7 +26,7 @@
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// updates output signals 1ns after the SPI clock edge.
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//
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// Supported commands:
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// AB, B9, FF, 03, EB, ED
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// AB, B9, FF, 03, BB, EB, ED
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//
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// Well written SPI flash data sheets:
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// Cypress S25FL064L http://www.cypress.com/file/316661/download
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@ -60,10 +60,12 @@ module spiflash (
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reg powered_up = 0;
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localparam [3:0] mode_spi = 1;
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localparam [3:0] mode_qspi_rd = 2;
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localparam [3:0] mode_qspi_wr = 3;
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localparam [3:0] mode_qspi_ddr_rd = 4;
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localparam [3:0] mode_qspi_ddr_wr = 5;
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localparam [3:0] mode_dspi_rd = 2;
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localparam [3:0] mode_dspi_wr = 3;
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localparam [3:0] mode_qspi_rd = 4;
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localparam [3:0] mode_qspi_wr = 5;
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localparam [3:0] mode_qspi_ddr_rd = 6;
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localparam [3:0] mode_qspi_ddr_wr = 7;
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reg [3:0] mode = 0;
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reg [3:0] next_mode = 0;
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@ -133,6 +135,31 @@ module spiflash (
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end
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end
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if (powered_up && spi_cmd == 'h bb) begin
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if (bytecount == 1)
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mode = mode_dspi_rd;
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if (bytecount == 2)
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spi_addr[23:16] = buffer;
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if (bytecount == 3)
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spi_addr[15:8] = buffer;
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if (bytecount == 4)
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spi_addr[7:0] = buffer;
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if (bytecount == 5) begin
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xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
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mode = mode_dspi_wr;
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dummycount = latency;
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end
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if (bytecount >= 5) begin
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buffer = memory[spi_addr];
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spi_addr = spi_addr + 1;
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end
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end
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if (powered_up && spi_cmd == 'h eb) begin
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if (bytecount == 1)
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mode = mode_qspi_rd;
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@ -269,6 +296,20 @@ module spiflash (
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io3_oe = 0;
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io1_dout = buffer[7];
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end
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mode_dspi_rd: begin
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io0_oe = 0;
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io1_oe = 0;
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io2_oe = 0;
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io3_oe = 0;
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end
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mode_dspi_wr: begin
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io0_oe = 1;
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io1_oe = 1;
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io2_oe = 0;
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io3_oe = 0;
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io0_dout = buffer[6];
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io1_dout = buffer[7];
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end
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mode_qspi_rd: begin
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io0_oe = 0;
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io1_oe = 0;
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@ -332,6 +373,15 @@ module spiflash (
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spi_action;
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end
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end
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mode_dspi_rd, mode_dspi_wr: begin
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buffer = {buffer, io1, io0};
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bitcount = bitcount + 2;
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if (bitcount == 8) begin
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bitcount = 0;
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bytecount = bytecount + 1;
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spi_action;
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end
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end
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mode_qspi_rd, mode_qspi_wr: begin
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buffer = {buffer, io3, io2, io1, io0};
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bitcount = bitcount + 4;
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@ -168,6 +168,9 @@ module spimemio (
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assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
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assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
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wire xfer_dspi = din_ddr && !din_qspi;
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wire xfer_ddr = din_ddr && din_qspi;
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spimemio_xfer xfer (
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.clk (clk ),
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.resetn (xfer_resetn ),
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@ -176,8 +179,9 @@ module spimemio (
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.din_data (din_data ),
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.din_tag (din_tag ),
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.din_cont (din_cont ),
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.din_dspi (xfer_dspi ),
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.din_qspi (din_qspi ),
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.din_ddr (din_ddr ),
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.din_ddr (xfer_ddr ),
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.din_rd (din_rd ),
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.dout_valid (dout_valid ),
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.dout_data (dout_data ),
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@ -266,6 +270,7 @@ module spimemio (
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case ({config_ddr, config_qspi})
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2'b11: din_data <= 8'h ED;
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2'b01: din_data <= 8'h EB;
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2'b10: din_data <= 8'h BB;
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2'b00: din_data <= 8'h 03;
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endcase
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if (din_ready) begin
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@ -302,7 +307,7 @@ module spimemio (
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if (din_ready) begin
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din_valid <= 0;
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din_data <= 0;
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state <= config_qspi ? 8 : 9;
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state <= config_qspi || config_ddr ? 8 : 9;
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end
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end
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8: begin
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@ -378,6 +383,7 @@ module spimemio_xfer (
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input [7:0] din_data,
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input [3:0] din_tag,
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input din_cont,
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input din_dspi,
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input din_qspi,
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input din_ddr,
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input din_rd,
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@ -411,6 +417,7 @@ module spimemio_xfer (
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reg [3:0] dummy_count;
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reg xfer_cont;
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reg xfer_dspi;
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reg xfer_qspi;
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reg xfer_ddr;
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reg xfer_ddr_q;
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@ -454,8 +461,8 @@ module spimemio_xfer (
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next_fetch = 0;
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if (dummy_count == 0) begin
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case ({xfer_ddr, xfer_qspi})
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2'b 00: begin
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casez ({xfer_ddr, xfer_qspi, xfer_dspi})
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3'b 000: begin
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flash_io0_oe = 1;
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flash_io0_do = obuffer[7];
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@ -468,7 +475,7 @@ module spimemio_xfer (
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next_fetch = (next_count == 0);
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end
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2'b 01: begin
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3'b 01?: begin
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flash_io0_oe = !xfer_rd;
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flash_io1_oe = !xfer_rd;
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flash_io2_oe = !xfer_rd;
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@ -488,7 +495,7 @@ module spimemio_xfer (
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next_fetch = (next_count == 0);
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end
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2'b 11: begin
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3'b 11?: begin
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flash_io0_oe = !xfer_rd;
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flash_io1_oe = !xfer_rd;
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flash_io2_oe = !xfer_rd;
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@ -503,6 +510,22 @@ module spimemio_xfer (
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next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
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next_count = count - {|count, 2'b00};
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next_fetch = (next_count == 0);
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end
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3'b ??1: begin
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flash_io0_oe = !xfer_rd;
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flash_io1_oe = !xfer_rd;
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flash_io0_do = obuffer[6];
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flash_io1_do = obuffer[7];
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if (flash_clk) begin
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next_obuffer = {obuffer[5:0], 2'b 00};
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next_count = count - {|count, 1'b0};
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end else begin
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next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di};
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end
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next_fetch = (next_count == 0);
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end
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endcase
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@ -519,6 +542,7 @@ module spimemio_xfer (
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dummy_count <= 0;
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xfer_tag <= 0;
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xfer_cont <= 0;
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xfer_dspi <= 0;
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xfer_qspi <= 0;
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xfer_ddr <= 0;
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xfer_rd <= 0;
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@ -545,6 +569,7 @@ module spimemio_xfer (
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xfer_tag <= din_tag;
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xfer_cont <= din_cont;
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xfer_dspi <= din_dspi;
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xfer_qspi <= din_qspi;
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xfer_ddr <= din_ddr;
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xfer_rd <= din_rd;
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